KEYMGR Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	52.930s	20.702ms	50	50	100.00
V1	random	keymgr_random	1.176m	7.512ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.140s	57.188us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.640s	34.094us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.750s	1.342ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	16.290s	1.842ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.220s	31.201us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.640s	34.094us	20	20	100.00
		keymgr_csr_aliasing	16.290s	1.842ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.307m	5.909ms	50	50	100.00
V2	sideload	keymgr_sideload	44.180s	6.492ms	49	50	98.00
		keymgr_sideload_kmac	1.021m	10.943ms	50	50	100.00
		keymgr_sideload_aes	47.170s	11.832ms	50	50	100.00
		keymgr_sideload_otbn	44.680s	7.286ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	34.590s	1.008ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	24.320s	7.041ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.690s	503.564us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.476m	11.200ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.602m	18.674ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	25.580s	3.066ms	48	50	96.00
V2	stress_all	keymgr_stress_all	8.486m	50.667ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.900s	14.288us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.000s	21.427us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.820s	692.025us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.820s	692.025us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.140s	57.188us	5	5	100.00
		keymgr_csr_rw	1.640s	34.094us	20	20	100.00
		keymgr_csr_aliasing	16.290s	1.842ms	5	5	100.00
		keymgr_same_csr_outstanding	4.830s	112.949us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.140s	57.188us	5	5	100.00
		keymgr_csr_rw	1.640s	34.094us	20	20	100.00
		keymgr_csr_aliasing	16.290s	1.842ms	5	5	100.00
		keymgr_same_csr_outstanding	4.830s	112.949us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
		keymgr_tl_intg_err	11.240s	1.394ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.700s	212.169us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.700s	212.169us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.700s	212.169us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.700s	212.169us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.820s	416.777us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.240s	1.394ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.700s	212.169us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.307m	5.909ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.176m	7.512ms	50	50	100.00
		keymgr_csr_rw	1.640s	34.094us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.176m	7.512ms	50	50	100.00
		keymgr_csr_rw	1.640s	34.094us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.176m	7.512ms	50	50	100.00
		keymgr_csr_rw	1.640s	34.094us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	24.320s	7.041ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.602m	18.674ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.602m	18.674ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.176m	7.512ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	24.330s	801.126us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	33.090s	1.297ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	24.320s	7.041ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	33.090s	1.297ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	33.090s	1.297ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	33.090s	1.297ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	15.920s	2.236ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	33.090s	1.297ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	30.260s	6.660ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1085	1110	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	10	62.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.04	97.87	98.35	100.00	99.02	98.41	91.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test keymgr_stress_all_with_rand_reset has 17 failures.
  - 5.keymgr_stress_all_with_rand_reset.16595391355925153507418259684774750434103344885002185359857727278434519715116
    Line 984, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 204728168 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 204728168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.keymgr_stress_all_with_rand_reset.70201018486970195940961521190256375403591951930467136327406232780137212084457
    Line 360, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 269309868 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 269309868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_sideload_otbn has 1 failures.
  - 4.keymgr_sideload_otbn.108878502881375479832992950501911253450798457832723108955005764706001726940082
    Line 339, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest/run.log
```
  UVM_ERROR @  50106520 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  50106520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 25.keymgr_stress_all.111707829850145396109835526870261435105128120829024197454510402800422325361530
    Line 1321, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 137264909 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 137264909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sideload has 1 failures.
  - 27.keymgr_sideload.77658548009911447550548967684173531184639746023072790789981972204184114111523
    Line 268, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_sideload/latest/run.log
```
  UVM_ERROR @   3244982 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   3244982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:262) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 25.keymgr_sync_async_fault_cross.14435929266065405847499305256933615457629763939788433486509553680114512758519
    Line 298, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  57034397 ps: (cip_base_scoreboard.sv:262) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  57034397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 33.keymgr_lc_disable.79029220747638006756693266552672822981513869153415118645606056489155524764178
    Line 382, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @ 136542621 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_2
  UVM_INFO @ 136542621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:755) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 42.keymgr_stress_all_with_rand_reset.40860640852907592419779120593190455182800068436038664843856265024431990751764
    Line 326, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 582177156 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 582177156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 45.keymgr_hwsw_invalid_input.69946906742892118587299121323774982363477502846397598843868867600081387254951
    Line 336, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  25155167 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  25155167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 46.keymgr_sync_async_fault_cross.7728711840692372822086702836717039593041930702727486853303341338812417612086
    Line 278, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @ 192051007 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] ||                 act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 192051007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KEYMGR Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`