d09e282b26
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 35.220s | 4.578ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 53.840s | 4.332ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.410s | 105.695us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.540s | 95.771us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 15.390s | 1.315ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 9.060s | 986.285us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.380s | 101.791us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.540s | 95.771us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 9.060s | 986.285us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.790m | 2.011ms | 49 | 50 | 98.00 |
V2 | sideload | keymgr_sideload | 31.730s | 1.535ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 40.230s | 1.772ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 31.020s | 3.061ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 46.460s | 1.766ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 33.780s | 1.366ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 45.280s | 2.802ms | 48 | 50 | 96.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 8.150s | 717.284us | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.577m | 8.201ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 26.710s | 4.974ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 31.600s | 5.850ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 5.532m | 12.047ms | 49 | 50 | 98.00 |
V2 | intr_test | keymgr_intr_test | 0.910s | 23.672us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.040s | 57.030us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 5.810s | 654.585us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 5.810s | 654.585us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.410s | 105.695us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.540s | 95.771us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 9.060s | 986.285us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.400s | 156.509us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.410s | 105.695us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.540s | 95.771us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 9.060s | 986.285us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.400s | 156.509us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 736 | 740 | 99.46 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 11.410s | 394.089us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 4.490s | 590.628us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 4.490s | 590.628us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 4.490s | 590.628us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 4.490s | 590.628us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 11.190s | 521.150us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 11.410s | 394.089us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 4.490s | 590.628us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.790m | 2.011ms | 49 | 50 | 98.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 53.840s | 4.332ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.540s | 95.771us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 53.840s | 4.332ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.540s | 95.771us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 53.840s | 4.332ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.540s | 95.771us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 45.280s | 2.802ms | 48 | 50 | 96.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 26.710s | 4.974ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 26.710s | 4.974ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 53.840s | 4.332ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 50.910s | 2.564ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 29.760s | 2.507ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 45.280s | 2.802ms | 48 | 50 | 96.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 29.760s | 2.507ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 29.760s | 2.507ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 29.760s | 2.507ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 19.660s | 913.874us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 29.760s | 2.507ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 26.700s | 3.342ms | 23 | 50 | 46.00 |
V3 | TOTAL | 23 | 50 | 46.00 | |||
TOTAL | 1079 | 1110 | 97.21 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 13 | 81.25 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.73 | 99.04 | 98.15 | 98.34 | 100.00 | 99.02 | 98.41 | 91.14 |
UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 26 failures:
0.keymgr_stress_all_with_rand_reset.62139750332475934432908212522784931625951480948229285018962348927618277985009
Line 487, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 854248772 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 854248772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.keymgr_stress_all_with_rand_reset.100609831213874294852954274319990328395096816344709912568918505945673031116946
Line 1275, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2095701691 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2095701691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 3 failures:
Test keymgr_lc_disable has 1 failures.
11.keymgr_lc_disable.103142695939310598698627706612388103165905981242419812073416358169144077689961
Line 353, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 48806705 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 48806705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_cfg_regwen has 1 failures.
33.keymgr_cfg_regwen.113951674267942247958562541679860281508084757437888593943606462537799957569192
Line 278, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 15136654 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 15136654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all has 1 failures.
36.keymgr_stress_all.79111564095832490556691597254255926112448139349731819809808727102365555627019
Line 836, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_stress_all/latest/run.log
UVM_ERROR @ 1106279026 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 1106279026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
27.keymgr_lc_disable.40276294292938739831968077139425802844054693139671485735149530889801993348813
Line 298, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 33310474 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_0
UVM_INFO @ 33310474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:771) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
has 1 failures:
41.keymgr_stress_all_with_rand_reset.5841842247177408192535023136346351666101465729181038298932393661626222001669
Line 328, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 109950399 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 109950399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---