KEYMGR Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.085m	22.909ms	50	50	100.00
V1	random	keymgr_random	42.170s	6.220ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.180s	29.905us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.510s	55.952us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	25.980s	881.179us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	12.920s	465.119us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.430s	65.109us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.510s	55.952us	20	20	100.00
		keymgr_csr_aliasing	12.920s	465.119us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.774m	4.136ms	50	50	100.00
V2	sideload	keymgr_sideload	35.110s	5.402ms	50	50	100.00
		keymgr_sideload_kmac	1.092m	6.662ms	50	50	100.00
		keymgr_sideload_aes	1.060m	16.463ms	50	50	100.00
		keymgr_sideload_otbn	26.610s	2.722ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	17.150s	1.882ms	49	50	98.00
V2	lc_disable	keymgr_lc_disable	15.430s	1.513ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	12.250s	1.104ms	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.014m	9.160ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.133m	3.780ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	20.590s	793.739us	50	50	100.00
V2	stress_all	keymgr_stress_all	2.752m	52.740ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.890s	15.360us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.030s	22.895us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.510s	155.526us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.510s	155.526us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.180s	29.905us	5	5	100.00
		keymgr_csr_rw	1.510s	55.952us	20	20	100.00
		keymgr_csr_aliasing	12.920s	465.119us	5	5	100.00
		keymgr_same_csr_outstanding	4.570s	2.191ms	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.180s	29.905us	5	5	100.00
		keymgr_csr_rw	1.510s	55.952us	20	20	100.00
		keymgr_csr_aliasing	12.920s	465.119us	5	5	100.00
		keymgr_same_csr_outstanding	4.570s	2.191ms	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
		keymgr_tl_intg_err	8.390s	445.261us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.670s	165.654us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.670s	165.654us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.670s	165.654us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.670s	165.654us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.910s	506.875us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.390s	445.261us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.670s	165.654us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.774m	4.136ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	42.170s	6.220ms	50	50	100.00
		keymgr_csr_rw	1.510s	55.952us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	42.170s	6.220ms	50	50	100.00
		keymgr_csr_rw	1.510s	55.952us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	42.170s	6.220ms	50	50	100.00
		keymgr_csr_rw	1.510s	55.952us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	15.430s	1.513ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.133m	3.780ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.133m	3.780ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	42.170s	6.220ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	16.750s	525.057us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	7.640s	472.234us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	15.430s	1.513ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	7.640s	472.234us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	7.640s	472.234us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	7.640s	472.234us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	37.530s	3.986ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	7.640s	472.234us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	27.320s	2.671ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			1089	1110	98.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.40	99.00	98.07	98.32	97.67	98.93	98.63	91.14

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

  • Test keymgr_stress_all_with_rand_reset has 14 failures.

    • 2.keymgr_stress_all_with_rand_reset.70964487966526222898431102051915509604765324478090460771111346048551009947162
      Line 487, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 393629948 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 393629948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.keymgr_stress_all_with_rand_reset.5961774816040999210853768199401164857911474434020697589365525391710673379158
      Line 438, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 500984136 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 500984136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

  • Test keymgr_stress_all_with_rand_reset has 2 failures.

    • 1.keymgr_stress_all_with_rand_reset.55240483825173000323102782489685591487119602156809392027489910125545028010188
      Line 393, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  54433369 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
        UVM_INFO @  54433369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 40.keymgr_stress_all_with_rand_reset.107717101342683280908179603694717964041859438249977760519479150467704336972412
      Line 1294, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 141881133 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 141881133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_direct_to_disabled has 1 failures.

    • 17.keymgr_direct_to_disabled.63485807541295582935275398277169983343254190259205569561708952945290818439343
      Line 477, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest/run.log

        UVM_ERROR @  14309464 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  14309464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 27.keymgr_stress_all.78871882063630994010851369453119828497591736095357922280778848461652062999704
      Line 708, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_stress_all/latest/run.log

        UVM_ERROR @  62113589 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  62113589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 2 failures:

  • Test keymgr_hwsw_invalid_input has 1 failures.

    • 7.keymgr_hwsw_invalid_input.9063862269541595542124650975309738107488308596503065733326611629188342433802
      Line 324, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest/run.log

        UVM_ERROR @  28340380 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  28340380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 15.keymgr_kmac_rsp_err.113014432760817140865145591007437683691199675225709336410363409294475182998637
      Line 499, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  19691365 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  19691365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 31.keymgr_stress_all.53747184103240250253857165551992551747334635526183615475482774921260407554652
      Line 2598, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/31.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 288680515 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
        UVM_INFO @ 288680515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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