KEYMGR Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 35.620s 7.542ms 50 50 100.00
V1 random keymgr_random 37.160s 2.355ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.340s 39.451us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.560s 41.393us 20 20 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 23.790s 5.121ms 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 11.860s 3.961ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 2.360s 82.031us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.560s 41.393us 20 20 100.00
keymgr_csr_aliasing 11.860s 3.961ms 5 5 100.00
V1 TOTAL 155 155 100.00
V2 cfgen_during_op keymgr_cfg_regwen 54.880s 4.384ms 50 50 100.00
V2 sideload keymgr_sideload 52.050s 2.740ms 50 50 100.00
keymgr_sideload_kmac 27.370s 1.254ms 50 50 100.00
keymgr_sideload_aes 30.670s 3.257ms 50 50 100.00
keymgr_sideload_otbn 40.470s 1.836ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 31.390s 1.250ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 34.060s 1.376ms 47 50 94.00
V2 kmac_error_response keymgr_kmac_rsp_err 5.160s 115.759us 49 50 98.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.002m 3.411ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 10.540s 496.064us 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 6.390s 192.990us 48 50 96.00
V2 stress_all keymgr_stress_all 3.907m 9.972ms 49 50 98.00
V2 intr_test keymgr_intr_test 0.950s 213.622us 50 50 100.00
V2 alert_test keymgr_alert_test 1.180s 114.537us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 5.070s 297.099us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 5.070s 297.099us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.340s 39.451us 5 5 100.00
keymgr_csr_rw 1.560s 41.393us 20 20 100.00
keymgr_csr_aliasing 11.860s 3.961ms 5 5 100.00
keymgr_same_csr_outstanding 4.320s 122.086us 20 20 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.340s 39.451us 5 5 100.00
keymgr_csr_rw 1.560s 41.393us 20 20 100.00
keymgr_csr_aliasing 11.860s 3.961ms 5 5 100.00
keymgr_same_csr_outstanding 4.320s 122.086us 20 20 100.00
V2 TOTAL 733 740 99.05
V2S sec_cm_additional_check keymgr_sec_cm 17.620s 956.200us 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 17.620s 956.200us 5 5 100.00
keymgr_tl_intg_err 10.420s 1.047ms 20 20 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 4.840s 349.424us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 4.840s 349.424us 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 4.840s 349.424us 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 4.840s 349.424us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 13.890s 363.156us 20 20 100.00
V2S prim_count_check keymgr_sec_cm 17.620s 956.200us 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 17.620s 956.200us 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 10.420s 1.047ms 20 20 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 4.840s 349.424us 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 54.880s 4.384ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 37.160s 2.355ms 50 50 100.00
keymgr_csr_rw 1.560s 41.393us 20 20 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 37.160s 2.355ms 50 50 100.00
keymgr_csr_rw 1.560s 41.393us 20 20 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 37.160s 2.355ms 50 50 100.00
keymgr_csr_rw 1.560s 41.393us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 34.060s 1.376ms 47 50 94.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 10.540s 496.064us 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 10.540s 496.064us 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 37.160s 2.355ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 34.430s 3.714ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 17.620s 956.200us 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 17.620s 956.200us 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 17.620s 956.200us 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 51.310s 6.694ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 34.060s 1.376ms 47 50 94.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 17.620s 956.200us 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 17.620s 956.200us 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 17.620s 956.200us 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 51.310s 6.694ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 51.310s 6.694ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 17.620s 956.200us 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 51.310s 6.694ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 17.620s 956.200us 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 51.310s 6.694ms 50 50 100.00
V2S TOTAL 165 165 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 29.690s 2.665ms 22 50 44.00
V3 TOTAL 22 50 44.00
TOTAL 1075 1110 96.85

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 16 16 12 75.00
V2S 6 6 6 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.43 99.00 98.03 98.47 97.67 98.93 98.63 91.24

Failure Buckets

Past Results