KEYMGR Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	35.620s	7.542ms	50	50	100.00
V1	random	keymgr_random	37.160s	2.355ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.340s	39.451us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.560s	41.393us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	23.790s	5.121ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	11.860s	3.961ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.360s	82.031us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.560s	41.393us	20	20	100.00
		keymgr_csr_aliasing	11.860s	3.961ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	54.880s	4.384ms	50	50	100.00
V2	sideload	keymgr_sideload	52.050s	2.740ms	50	50	100.00
		keymgr_sideload_kmac	27.370s	1.254ms	50	50	100.00
		keymgr_sideload_aes	30.670s	3.257ms	50	50	100.00
		keymgr_sideload_otbn	40.470s	1.836ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	31.390s	1.250ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	34.060s	1.376ms	47	50	94.00
V2	kmac_error_response	keymgr_kmac_rsp_err	5.160s	115.759us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.002m	3.411ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	10.540s	496.064us	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	6.390s	192.990us	48	50	96.00
V2	stress_all	keymgr_stress_all	3.907m	9.972ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.950s	213.622us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.180s	114.537us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.070s	297.099us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.070s	297.099us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.340s	39.451us	5	5	100.00
		keymgr_csr_rw	1.560s	41.393us	20	20	100.00
		keymgr_csr_aliasing	11.860s	3.961ms	5	5	100.00
		keymgr_same_csr_outstanding	4.320s	122.086us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.340s	39.451us	5	5	100.00
		keymgr_csr_rw	1.560s	41.393us	20	20	100.00
		keymgr_csr_aliasing	11.860s	3.961ms	5	5	100.00
		keymgr_same_csr_outstanding	4.320s	122.086us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
		keymgr_tl_intg_err	10.420s	1.047ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.840s	349.424us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.840s	349.424us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.840s	349.424us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.840s	349.424us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.890s	363.156us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.420s	1.047ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.840s	349.424us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	54.880s	4.384ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	37.160s	2.355ms	50	50	100.00
		keymgr_csr_rw	1.560s	41.393us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	37.160s	2.355ms	50	50	100.00
		keymgr_csr_rw	1.560s	41.393us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	37.160s	2.355ms	50	50	100.00
		keymgr_csr_rw	1.560s	41.393us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	34.060s	1.376ms	47	50	94.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	10.540s	496.064us	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	10.540s	496.064us	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	37.160s	2.355ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	34.430s	3.714ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	51.310s	6.694ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	34.060s	1.376ms	47	50	94.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	51.310s	6.694ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	51.310s	6.694ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	51.310s	6.694ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.620s	956.200us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	51.310s	6.694ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	29.690s	2.665ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1075	1110	96.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.43	99.00	98.03	98.47	97.67	98.93	98.63	91.24

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test keymgr_stress_all_with_rand_reset has 28 failures.
  - 0.keymgr_stress_all_with_rand_reset.97245454265253274487310891693254276688137420173539622856472894403555560937744
    Line 290, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 424634429 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 424634429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.keymgr_stress_all_with_rand_reset.99880560547056031223508174051404052260206886304091205154006180222947069790065
    Line 1383, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 456600822 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 456600822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
UVM_ERROR (cip_base_scoreboard.sv:262) scoreboard [scoreboard] alert recov_operation_err is not received! has 2 failures:
- Test keymgr_sync_async_fault_cross has 2 failures.
  - 7.keymgr_sync_async_fault_cross.34988557799128899314397070670053443063806859356923985598862116198575606552090
    Line 319, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  90993684 ps: (cip_base_scoreboard.sv:262) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  90993684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.keymgr_sync_async_fault_cross.101791878487331982372218359358835815320548078523178004979404245814414492645056
    Line 355, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @ 335278230 ps: (cip_base_scoreboard.sv:262) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @ 335278230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Attestation Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

5.keymgr_lc_disable.9126955433847297340687393317808713077803270352159344601101474149575289326092
Line 548, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 232691090 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2485196682483656742782846797147155265928762741488871363687923194021118439989644448785257292177567203110629014705668037070998543824360460008570562231230218 [0x2f73636a97c8981ba387d7558e57680335fee21b96336f9fd102b185c44e25a19d34aa6f9697d311422149819727b3aaad49ea5dc143f371f18f75432e015f0a] vs 2485196682483656742782846797147155265928762741488871363687923194021118439989644448785257292177567203110629014705668037070998543824360460008570562231230218 [0x2f73636a97c8981ba387d7558e57680335fee21b96336f9fd102b185c44e25a19d34aa6f9697d311422149819727b3aaad49ea5dc143f371f18f75432e015f0a]) KMAC key at state StDisabled for Attestation Kmac
  UVM_INFO @ 232691090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 9.keymgr_lc_disable.110805215979486037957726848437804445657869126112498783567674090285450363881230
    Line 400, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  16539688 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
  UVM_INFO @  16539688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 15.keymgr_stress_all.108463734437426232312422677690888646066006388530383988534734105614711385561765
    Line 271, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @  38870584 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_2
  UVM_INFO @  38870584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 28.keymgr_lc_disable.21271146151662589708433962861689065823089528469654989970486961348343373400424
    Line 392, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/28.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @ 837049113 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_2
  UVM_INFO @ 837049113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 45.keymgr_kmac_rsp_err.96100025507562073579797956130896780847694901918103452255407495964975292645487
    Line 507, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  27037544 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  27037544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```