KEYMGR Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	49.480s	5.440ms	50	50	100.00
V1	random	keymgr_random	34.770s	2.823ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.430s	77.977us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.440s	90.972us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	14.530s	1.087ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	15.240s	431.111us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.290s	36.164us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.440s	90.972us	20	20	100.00
		keymgr_csr_aliasing	15.240s	431.111us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.437m	8.034ms	48	50	96.00
V2	sideload	keymgr_sideload	39.950s	2.023ms	50	50	100.00
		keymgr_sideload_kmac	40.970s	1.526ms	50	50	100.00
		keymgr_sideload_aes	33.080s	5.301ms	50	50	100.00
		keymgr_sideload_otbn	43.770s	1.704ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	16.700s	494.724us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	25.460s	1.681ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	20.860s	1.453ms	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	56.260s	6.188ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	32.030s	5.283ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	24.300s	4.711ms	50	50	100.00
V2	stress_all	keymgr_stress_all	2.579m	111.312ms	46	50	92.00
V2	intr_test	keymgr_intr_test	0.940s	51.708us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.000s	31.311us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.600s	236.052us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.600s	236.052us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.430s	77.977us	5	5	100.00
		keymgr_csr_rw	1.440s	90.972us	20	20	100.00
		keymgr_csr_aliasing	15.240s	431.111us	5	5	100.00
		keymgr_same_csr_outstanding	4.130s	123.232us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.430s	77.977us	5	5	100.00
		keymgr_csr_rw	1.440s	90.972us	20	20	100.00
		keymgr_csr_aliasing	15.240s	431.111us	5	5	100.00
		keymgr_same_csr_outstanding	4.130s	123.232us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
		keymgr_tl_intg_err	10.810s	538.572us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.690s	228.796us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.690s	228.796us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.690s	228.796us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.690s	228.796us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.790s	605.485us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.810s	538.572us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.690s	228.796us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.437m	8.034ms	48	50	96.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	34.770s	2.823ms	50	50	100.00
		keymgr_csr_rw	1.440s	90.972us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	34.770s	2.823ms	50	50	100.00
		keymgr_csr_rw	1.440s	90.972us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	34.770s	2.823ms	50	50	100.00
		keymgr_csr_rw	1.440s	90.972us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	25.460s	1.681ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	32.030s	5.283ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	32.030s	5.283ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	34.770s	2.823ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	25.750s	1.485ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	20.960s	1.818ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	25.460s	1.681ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	20.960s	1.818ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	20.960s	1.818ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	20.960s	1.818ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.830s	2.534ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	20.960s	1.818ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.580s	1.221ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1079	1110	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.04	98.07	98.37	100.00	99.02	98.63	91.27

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test keymgr_stress_all_with_rand_reset has 24 failures.
  - 2.keymgr_stress_all_with_rand_reset.6722724243012660189635113714673708051101044920756282163914103650824205796154
    Line 355, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 473868633 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 473868633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.keymgr_stress_all_with_rand_reset.101638937085423037556256259401810939030947939618582409826471132269254117053665
    Line 290, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107716667 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 107716667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.

UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_stress_all has 2 failures.

23.keymgr_stress_all.79289696085390315511995813208119703426084885956213123531367436546354445811623
Line 972, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 222039469 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 222039469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.keymgr_stress_all.51857341689918240303614185607601062532009502506688473899358861631730030071758
Line 1099, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 365545958 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 365545958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_cfg_regwen has 1 failures.

32.keymgr_cfg_regwen.39767740891509472773301035721274401849051085075504188731220645201634232529833
Line 273, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @   8366132 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   8366132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 2.keymgr_stress_all.68644129543635525476150448022893706703926487874026298806360924215562888003668
    Line 2402, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 10728938965 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 3 [0x3])
  UVM_INFO @ 10728938965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 20.keymgr_kmac_rsp_err.14771302816050577056417599043457360064713633655858351147283587234260817847441
    Line 443, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  70051171 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  70051171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 40.keymgr_stress_all.97028715398930439755423397514280630141245945878844656675483371373776674425069
    Line 1387, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1428988760 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_1
  UVM_INFO @ 1428988760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 41.keymgr_cfg_regwen.33874736524610647460059770506014250332736316167441463225237130951670551819161
    Line 345, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @   8241425 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @   8241425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```