KEYMGR Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 32.160s 2.242ms 50 50 100.00
V1 random keymgr_random 1.322m 8.944ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.200s 112.433us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.530s 29.579us 20 20 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 16.320s 4.480ms 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 9.610s 1.065ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 2.020s 29.842us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.530s 29.579us 20 20 100.00
keymgr_csr_aliasing 9.610s 1.065ms 5 5 100.00
V1 TOTAL 155 155 100.00
V2 cfgen_during_op keymgr_cfg_regwen 57.740s 2.813ms 50 50 100.00
V2 sideload keymgr_sideload 30.540s 2.865ms 50 50 100.00
keymgr_sideload_kmac 1.130m 6.166ms 50 50 100.00
keymgr_sideload_aes 1.173m 5.569ms 50 50 100.00
keymgr_sideload_otbn 33.490s 4.528ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 10.420s 341.928us 50 50 100.00
V2 lc_disable keymgr_lc_disable 13.780s 919.060us 50 50 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 16.530s 924.381us 50 50 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 47.310s 17.301ms 49 50 98.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 20.630s 821.563us 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 16.890s 6.201ms 50 50 100.00
V2 stress_all keymgr_stress_all 11.197m 23.364ms 49 50 98.00
V2 intr_test keymgr_intr_test 0.970s 19.246us 50 50 100.00
V2 alert_test keymgr_alert_test 1.040s 293.746us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 6.090s 688.423us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 6.090s 688.423us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.200s 112.433us 5 5 100.00
keymgr_csr_rw 1.530s 29.579us 20 20 100.00
keymgr_csr_aliasing 9.610s 1.065ms 5 5 100.00
keymgr_same_csr_outstanding 3.690s 217.473us 20 20 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.200s 112.433us 5 5 100.00
keymgr_csr_rw 1.530s 29.579us 20 20 100.00
keymgr_csr_aliasing 9.610s 1.065ms 5 5 100.00
keymgr_same_csr_outstanding 3.690s 217.473us 20 20 100.00
V2 TOTAL 738 740 99.73
V2S sec_cm_additional_check keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
keymgr_tl_intg_err 10.870s 582.288us 20 20 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 4.360s 186.576us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 4.360s 186.576us 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 4.360s 186.576us 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 4.360s 186.576us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 13.390s 796.329us 20 20 100.00
V2S prim_count_check keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 10.870s 582.288us 20 20 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 4.360s 186.576us 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 57.740s 2.813ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 1.322m 8.944ms 50 50 100.00
keymgr_csr_rw 1.530s 29.579us 20 20 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 1.322m 8.944ms 50 50 100.00
keymgr_csr_rw 1.530s 29.579us 20 20 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 1.322m 8.944ms 50 50 100.00
keymgr_csr_rw 1.530s 29.579us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 13.780s 919.060us 50 50 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 20.630s 821.563us 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 20.630s 821.563us 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 1.322m 8.944ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 30.370s 1.196ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 33.750s 3.578ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 13.780s 919.060us 50 50 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 33.750s 3.578ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 33.750s 3.578ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 33.750s 3.578ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 12.400s 2.290ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 33.750s 3.578ms 50 50 100.00
V2S TOTAL 165 165 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 29.000s 727.539us 26 50 52.00
V3 TOTAL 26 50 52.00
TOTAL 1084 1110 97.66

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 16 16 14 87.50
V2S 6 6 6 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.78 99.04 97.91 98.66 100.00 99.02 98.63 91.22

Failure Buckets

Past Results