KEYMGR Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	32.160s	2.242ms	50	50	100.00
V1	random	keymgr_random	1.322m	8.944ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.200s	112.433us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.530s	29.579us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.320s	4.480ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.610s	1.065ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.020s	29.842us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.530s	29.579us	20	20	100.00
		keymgr_csr_aliasing	9.610s	1.065ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	57.740s	2.813ms	50	50	100.00
V2	sideload	keymgr_sideload	30.540s	2.865ms	50	50	100.00
		keymgr_sideload_kmac	1.130m	6.166ms	50	50	100.00
		keymgr_sideload_aes	1.173m	5.569ms	50	50	100.00
		keymgr_sideload_otbn	33.490s	4.528ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	10.420s	341.928us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	13.780s	919.060us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	16.530s	924.381us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	47.310s	17.301ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	20.630s	821.563us	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	16.890s	6.201ms	50	50	100.00
V2	stress_all	keymgr_stress_all	11.197m	23.364ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.970s	19.246us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.040s	293.746us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	6.090s	688.423us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	6.090s	688.423us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.200s	112.433us	5	5	100.00
		keymgr_csr_rw	1.530s	29.579us	20	20	100.00
		keymgr_csr_aliasing	9.610s	1.065ms	5	5	100.00
		keymgr_same_csr_outstanding	3.690s	217.473us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.200s	112.433us	5	5	100.00
		keymgr_csr_rw	1.530s	29.579us	20	20	100.00
		keymgr_csr_aliasing	9.610s	1.065ms	5	5	100.00
		keymgr_same_csr_outstanding	3.690s	217.473us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
		keymgr_tl_intg_err	10.870s	582.288us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.360s	186.576us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.360s	186.576us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.360s	186.576us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.360s	186.576us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.390s	796.329us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.870s	582.288us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.360s	186.576us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	57.740s	2.813ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.322m	8.944ms	50	50	100.00
		keymgr_csr_rw	1.530s	29.579us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.322m	8.944ms	50	50	100.00
		keymgr_csr_rw	1.530s	29.579us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.322m	8.944ms	50	50	100.00
		keymgr_csr_rw	1.530s	29.579us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	13.780s	919.060us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	20.630s	821.563us	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	20.630s	821.563us	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.322m	8.944ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	30.370s	1.196ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	33.750s	3.578ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	13.780s	919.060us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	33.750s	3.578ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	33.750s	3.578ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	33.750s	3.578ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.400s	2.290ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	33.750s	3.578ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	29.000s	727.539us	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1084	1110	97.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.04	97.91	98.66	100.00	99.02	98.63	91.22

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test keymgr_stress_all_with_rand_reset has 22 failures.
  - 1.keymgr_stress_all_with_rand_reset.66658917845506714520542105454065560314944169353361436603313164700883769247475
    Line 271, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 346738354 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 346738354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.109847063412484426430669820757075233439172594518454013197083821892881745435590
    Line 297, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 205636343 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 205636343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 5.keymgr_stress_all_with_rand_reset.9960236395694471464203781213489521296354712149835526047237641739302937392601
    Line 1605, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 296780241 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (973175192 [0x3a017998] vs 973175192 [0x3a017998]) reg name: keymgr_reg_block.sw_share1_output_2
  UVM_INFO @ 296780241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

18.keymgr_stress_all.35156209636433575466239792733953716288279971114809118332231870239141552947809
Line 629, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/18.keymgr_stress_all/latest/run.log

  UVM_ERROR @  45068824 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (12342701060455427316637918645109841975157016534628362571201937017450358338295301784473704078445256709917488680230758099535125059078628922163639831423433323 [0xeba9ddb6b9cf03b7b5aa839dd94054e9dde8bd554d35cf52ca2c0ecd19baf8c2b4b22ac4ae83e61a2e9494baf939db0708d0c88123dabd3abecb8fe60bc13a6b] vs 12342701060455427316637918645109841975157016534628362571201937017450358338295301784473704078445256709917488680230758099535125059078628922163639831423433323 [0xeba9ddb6b9cf03b7b5aa839dd94054e9dde8bd554d35cf52ca2c0ecd19baf8c2b4b22ac4ae83e61a2e9494baf939db0708d0c88123dabd3abecb8fe60bc13a6b]) AES key at state StCreatorRootKey for Attestation Aes
  UVM_INFO @  45068824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

22.keymgr_stress_all_with_rand_reset.10579145666893827938982951724438748796824759162777383291064719460432276195677
Line 1621, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 415159056 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (25218972382928738027255969608578339865916491315243043306183934009355370347637347649310378614807116357444007197460774391775545164211881185207234596365802617388502554326602637445440583660299443163142626067066266899336086950364263614815962917071464005447977358505985934748834273035090280473653593543644215764229139652402596943835459806969411080991481 [0x6989f1e57b59eb3c64e71651704773bda9acd48fba57cea2d6407bf62c94761c000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f5073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9] vs 11762259337641150210993494718804255115246482931741990978510803826515118917005955023680243780542953989404492416688481098216141566790273722462178879666156075557861114103394002451926234498805480795862302714899965559997624088734365102428569837065816347137732767934119903576327365046344176491679896488615521857121897960498968992517376165266717726126841 [0x31394f37833b064948cf44cd2668ee5ea27692bca7d05c8b953ed0cc65479b89000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f5073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9]) cdi_type: Attestation
  
   HardwareRevisionSecret act: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9, exp: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9
   RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e

UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_sw_invalid_input has 1 failures.
  - 25.keymgr_sw_invalid_input.10277181708620688129523498463637980911674529236890012868237389896255484162136
    Line 319, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest/run.log
```
  UVM_ERROR @   9428581 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   9428581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```