KEYMGR Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	35.170s	1.788ms	50	50	100.00
V1	random	keymgr_random	30.260s	3.240ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.170s	33.248us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.190s	97.467us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.760s	7.555ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	14.040s	552.383us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.040s	141.403us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.190s	97.467us	20	20	100.00
		keymgr_csr_aliasing	14.040s	552.383us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.087m	12.770ms	50	50	100.00
V2	sideload	keymgr_sideload	26.580s	872.981us	50	50	100.00
		keymgr_sideload_kmac	38.890s	1.700ms	50	50	100.00
		keymgr_sideload_aes	28.350s	3.189ms	50	50	100.00
		keymgr_sideload_otbn	54.070s	6.498ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	18.970s	2.311ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	6.960s	283.924us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	12.240s	1.550ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	50.360s	5.568ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.268m	5.283ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	13.460s	2.204ms	47	50	94.00
V2	stress_all	keymgr_stress_all	3.172m	34.156ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.890s	29.454us	50	50	100.00
V2	alert_test	keymgr_alert_test	0.910s	22.783us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.620s	164.077us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.620s	164.077us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.170s	33.248us	5	5	100.00
		keymgr_csr_rw	1.190s	97.467us	20	20	100.00
		keymgr_csr_aliasing	14.040s	552.383us	5	5	100.00
		keymgr_same_csr_outstanding	3.450s	127.385us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.170s	33.248us	5	5	100.00
		keymgr_csr_rw	1.190s	97.467us	20	20	100.00
		keymgr_csr_aliasing	14.040s	552.383us	5	5	100.00
		keymgr_same_csr_outstanding	3.450s	127.385us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
		keymgr_tl_intg_err	8.830s	2.343ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.040s	216.074us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.040s	216.074us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.040s	216.074us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.040s	216.074us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.180s	467.832us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.830s	2.343ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.040s	216.074us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.087m	12.770ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	30.260s	3.240ms	50	50	100.00
		keymgr_csr_rw	1.190s	97.467us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	30.260s	3.240ms	50	50	100.00
		keymgr_csr_rw	1.190s	97.467us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	30.260s	3.240ms	50	50	100.00
		keymgr_csr_rw	1.190s	97.467us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	6.960s	283.924us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.268m	5.283ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.268m	5.283ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	30.260s	3.240ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	23.480s	6.565ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	16.860s	10.066ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	6.960s	283.924us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	16.860s	10.066ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	16.860s	10.066ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	16.860s	10.066ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.020s	1.175ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	16.860s	10.066ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	22.770s	2.611ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1079	1110	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.88	99.04	98.11	99.20	100.00	99.02	98.63	91.19

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test keymgr_stress_all_with_rand_reset has 22 failures.
  - 3.keymgr_stress_all_with_rand_reset.50602067614704294638698384523560137157112396402956200032073313652660492744229
    Line 266, in log /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 143005067 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 143005067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.keymgr_stress_all_with_rand_reset.86110752642353479049162955596638780164062026181179425313851439787265089869468
    Line 301, in log /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127335843 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 127335843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:
- Test keymgr_stress_all_with_rand_reset has 2 failures.
  - 8.keymgr_stress_all_with_rand_reset.34344670912414706322662891242917587786872922227361816034015986694160690372536
    Line 1933, in log /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 352196899 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 352196899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.keymgr_stress_all_with_rand_reset.106517647929291818378804558493406651079904334949802705868497871888812758646911
    Line 223, in log /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 165785556 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 165785556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 21.keymgr_sync_async_fault_cross.8817972673402691357800897668887059343004109577342563325484376516281674487243
    Line 76, in log /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @   3918368 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   3918368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_lc_disable has 1 failures.
  - 24.keymgr_lc_disable.57791659981346306343317697870557245824067182844038243042452863079672585512390
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  40665202 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @  40665202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:262) scoreboard [scoreboard] alert recov_operation_err is not received! has 2 failures:
- Test keymgr_sync_async_fault_cross has 2 failures.
  - 1.keymgr_sync_async_fault_cross.8059812859286318834626038475500371449955828837165412888488402082081594985784
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  46242274 ps: (cip_base_scoreboard.sv:262) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  46242274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.keymgr_sync_async_fault_cross.103926268399851628452767014859817799890990428682022564051825219614793328256148
    Line 124, in log /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  77617775 ps: (cip_base_scoreboard.sv:262) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  77617775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout keymgr_reg_block.working_state (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 6.keymgr_custom_cm.2699105739132344723789325949579627265853478385094287162105816138957330959716
    Line 227, in log /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 10066380670 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout keymgr_reg_block.working_state (addr=0xbe5328e8, Comparison=CompareOpEq, exp_data=0x5, call_count=3)
  UVM_INFO @ 10066380670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_binding_regwen` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 9.keymgr_stress_all_with_rand_reset.48927694272520028416404729036035251939563286071874895260764262878729380022833
    Line 2076, in log /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 450334610 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.sw_binding_regwen
  UVM_INFO @ 450334610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Attestation Kmac has 1 failures:

Test keymgr_stress_all has 1 failures.

47.keymgr_stress_all.8035777107490267807362850886161474127763629257922551073339179229303885213541
Line 2393, in log /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 871183479 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (8031913927299249996382219491408100071508929687164388194832720580989423413592579237014514638116263586545762819656658844825559070463035287003624794459564113 [0x995b2d6f5470cbb4e33e06ef2282db5af8b894714d07be8621e5f4bee03a0d5bd292b52ab4689e0112dcefb1a93e8b428aa98bc9af23b5e0ecceec1ab2216851] vs 8031913927299249996382219491408100071508929687164388194832720580989423413592579237014514638116263586545762819656658844825559070463035287003624794459564113 [0x995b2d6f5470cbb4e33e06ef2282db5af8b894714d07be8621e5f4bee03a0d5bd292b52ab4689e0112dcefb1a93e8b428aa98bc9af23b5e0ecceec1ab2216851]) KMAC key at state StDisabled for Attestation Kmac
  UVM_INFO @ 871183479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---