KEYMGR Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 30.870s 2.823ms 50 50 100.00
V1 random keymgr_random 1.047m 2.250ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.720s 20.068us 5 5 100.00
V1 csr_rw keymgr_csr_rw 2.380s 53.593us 20 20 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 36.300s 3.579ms 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 23.880s 2.026ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 3.600s 51.455us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 2.380s 53.593us 20 20 100.00
keymgr_csr_aliasing 23.880s 2.026ms 5 5 100.00
V1 TOTAL 155 155 100.00
V2 cfgen_during_op keymgr_cfg_regwen 2.131m 7.117ms 50 50 100.00
V2 sideload keymgr_sideload 58.300s 6.394ms 50 50 100.00
keymgr_sideload_kmac 1.843m 9.599ms 50 50 100.00
keymgr_sideload_aes 1.067m 3.518ms 50 50 100.00
keymgr_sideload_otbn 1.337m 17.659ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 13.990s 363.360us 50 50 100.00
V2 lc_disable keymgr_lc_disable 39.120s 594.348us 49 50 98.00
V2 kmac_error_response keymgr_kmac_rsp_err 8.710s 510.620us 50 50 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.879m 8.641ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.294m 28.752ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 20.070s 561.059us 49 50 98.00
V2 stress_all keymgr_stress_all 3.837m 9.869ms 47 50 94.00
V2 intr_test keymgr_intr_test 1.560s 22.035us 50 50 100.00
V2 alert_test keymgr_alert_test 1.530s 73.313us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 6.690s 430.569us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 6.690s 430.569us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.720s 20.068us 5 5 100.00
keymgr_csr_rw 2.380s 53.593us 20 20 100.00
keymgr_csr_aliasing 23.880s 2.026ms 5 5 100.00
keymgr_same_csr_outstanding 5.690s 1.006ms 20 20 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.720s 20.068us 5 5 100.00
keymgr_csr_rw 2.380s 53.593us 20 20 100.00
keymgr_csr_aliasing 23.880s 2.026ms 5 5 100.00
keymgr_same_csr_outstanding 5.690s 1.006ms 20 20 100.00
V2 TOTAL 735 740 99.32
V2S sec_cm_additional_check keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
keymgr_tl_intg_err 13.710s 441.519us 20 20 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 6.450s 131.956us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 6.450s 131.956us 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 6.450s 131.956us 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 6.450s 131.956us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 22.690s 7.030ms 20 20 100.00
V2S prim_count_check keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 13.710s 441.519us 20 20 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 6.450s 131.956us 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.131m 7.117ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 1.047m 2.250ms 50 50 100.00
keymgr_csr_rw 2.380s 53.593us 20 20 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 1.047m 2.250ms 50 50 100.00
keymgr_csr_rw 2.380s 53.593us 20 20 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 1.047m 2.250ms 50 50 100.00
keymgr_csr_rw 2.380s 53.593us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 39.120s 594.348us 49 50 98.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.294m 28.752ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.294m 28.752ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 1.047m 2.250ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 26.090s 1.624ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 45.470s 2.282ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 39.120s 594.348us 49 50 98.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 45.470s 2.282ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 45.470s 2.282ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 45.470s 2.282ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 24.460s 1.114ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 45.470s 2.282ms 50 50 100.00
V2S TOTAL 165 165 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 44.080s 10.848ms 24 50 48.00
V3 TOTAL 24 50 48.00
TOTAL 1079 1110 97.21

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 16 16 13 81.25
V2S 6 6 6 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.79 99.04 98.11 98.60 100.00 99.02 98.63 91.12

Failure Buckets

Past Results