KEYMGR Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	45.030s	6.910ms	50	50	100.00
V1	random	keymgr_random	35.240s	7.347ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.410s	190.312us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	41.974s		19	20	95.00
V1	csr_bit_bash	keymgr_csr_bit_bash	15.310s	2.401ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	48.355s		4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	48.888s		18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	41.974s		19	20	95.00
		keymgr_csr_aliasing	48.355s		4	5	80.00
V1		TOTAL			151	155	97.42
V2	cfgen_during_op	keymgr_cfg_regwen	50.210s	1.072ms	50	50	100.00
V2	sideload	keymgr_sideload	41.630s		49	50	98.00
		keymgr_sideload_kmac	32.470s	2.954ms	50	50	100.00
		keymgr_sideload_aes	41.460s	1.805ms	50	50	100.00
		keymgr_sideload_otbn	49.110s	6.257ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	34.340s	3.743ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	13.160s	1.974ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	18.310s	4.802ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	55.680s	2.142ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	43.780s	3.499ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	17.700s	1.229ms	49	50	98.00
V2	stress_all	keymgr_stress_all	5.298m	51.438ms	46	50	92.00
V2	intr_test	keymgr_intr_test	43.002s		49	50	98.00
V2	alert_test	keymgr_alert_test	41.680s		49	50	98.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	42.987s		18	20	90.00
V2	tl_d_illegal_access	keymgr_tl_errors	42.987s		18	20	90.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.410s	190.312us	5	5	100.00
		keymgr_csr_rw	41.974s		19	20	95.00
		keymgr_csr_aliasing	48.355s		4	5	80.00
		keymgr_same_csr_outstanding	42.938s		18	20	90.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.410s	190.312us	5	5	100.00
		keymgr_csr_rw	41.974s		19	20	95.00
		keymgr_csr_aliasing	48.355s		4	5	80.00
		keymgr_same_csr_outstanding	42.938s		18	20	90.00
V2		TOTAL			727	740	98.24
V2S	sec_cm_additional_check	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
		keymgr_tl_intg_err	8.280s	1.048ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	42.054s		18	20	90.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	42.054s		18	20	90.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	42.054s		18	20	90.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	42.054s		18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.027m		18	20	90.00
V2S	prim_count_check	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.280s	1.048ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	42.054s		18	20	90.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	50.210s	1.072ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	35.240s	7.347ms	50	50	100.00
		keymgr_csr_rw	41.974s		19	20	95.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	35.240s	7.347ms	50	50	100.00
		keymgr_csr_rw	41.974s		19	20	95.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	35.240s	7.347ms	50	50	100.00
		keymgr_csr_rw	41.974s		19	20	95.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	13.160s	1.974ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	43.780s	3.499ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	43.780s	3.499ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	35.240s	7.347ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	27.850s	2.952ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	35.870s	1.508ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	13.160s	1.974ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	35.870s	1.508ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	35.870s	1.508ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	35.870s	1.508ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	1.039m	3.018ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	35.870s	1.508ms	50	50	100.00
V2S		TOTAL			160	165	96.97
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.360s	2.333ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1071	1110	96.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	4	57.14
V2	16	16	8	50.00
V2S	6	6	3	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.04	98.11	98.17	100.00	99.02	98.63	91.09

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test keymgr_stress_all_with_rand_reset has 16 failures.
  - 4.keymgr_stress_all_with_rand_reset.113696750337304353426377941842525483059845025122231035654831071199516702857305
    Line 204, in log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 508688707 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 508688707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.keymgr_stress_all_with_rand_reset.76628508838464792840373466834268321451945737811442092379486547480014439416980
    Line 657, in log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 324752583 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 324752583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.

Job returned non-zero exit code has 15 failures:

Test keymgr_csr_mem_rw_with_rand_reset has 2 failures.

0.keymgr_csr_mem_rw_with_rand_reset.26351901143571670226450176824003717985170924340910278207961524406998895311037
Log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:35 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

4.keymgr_csr_mem_rw_with_rand_reset.115598855869433115470834635292403964624441871624213916919120045295653158521489
Log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:35 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test keymgr_csr_aliasing has 1 failures.

4.keymgr_csr_aliasing.56611444725884500512886902903353384725882871913953960401386696242980186250991
Log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:35 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test keymgr_same_csr_outstanding has 2 failures.

4.keymgr_same_csr_outstanding.31443007136042891045083884417887869336190089622659529836683403068395527626471
Log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:35 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

5.keymgr_same_csr_outstanding.63115954866724413801005981383314294364430619825811088595037353213429542550186
Log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:35 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test keymgr_tl_errors has 2 failures.

5.keymgr_tl_errors.1962914452322681413414107560334704327012713142247009554220510637483037123110
Log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_tl_errors/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:35 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

8.keymgr_tl_errors.111428415260859926409606443203924953353874191047539911279116010185515188127265
Log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_tl_errors/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:35 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test keymgr_intr_test has 1 failures.

5.keymgr_intr_test.102950659387980580551456463160147296724322695039473907553004839462369206254994
Log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_intr_test/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:35 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 5 more tests.

UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:
- Test keymgr_sw_invalid_input has 1 failures.
  - 13.keymgr_sw_invalid_input.100647192783616965557894900375468251103529581266841839066409266147762427558305
    Line 168, in log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest/run.log
```
  UVM_ERROR @  40197641 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  40197641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 32.keymgr_sync_async_fault_cross.93185268317134846540900581257555170515436823971333681540212744016809692976261
    Line 85, in log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  12104104 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  12104104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 34.keymgr_stress_all.28586854777608700992553557010704916278042000082997061109716748059167693444969
    Line 1348, in log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 580210583 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 580210583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sideload_protect has 1 failures.
  - 39.keymgr_sideload_protect.95795017722832556104321973310071581382380511381616370729835406473200881098022
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_sideload_protect/latest/run.log
```
  UVM_ERROR @  17230828 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  17230828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 2 failures:
- Test keymgr_stress_all has 2 failures.
  - 32.keymgr_stress_all.67062033127234391139774706929140397560664285986243077417025154492090101880940
    Line 2054, in log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 2874695401 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_4
  UVM_INFO @ 2874695401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.keymgr_stress_all.22983877907822769437011780963680292109073459459832706956561731274012145931324
    Line 1242, in log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 449956197 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_5
  UVM_INFO @ 449956197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Sealing Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

12.keymgr_stress_all.12827235223922512656768242340190234973774145793083988029836074645155026667236
Line 1488, in log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 453679581 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (7901141985504465324020819026719246443385844477385088676696326300446558031780197028589297378605095939742913766764573396746118478089429324031259540383687604 [0x96dbfa404a8b5d59c53dc701f0deb40127d3bc74cd60b35fb77d6d404987ee250a1bfca32a81027abe24d7ed739f20444a245791c84297aede08fd0c7e1963b4] vs 7901141985504465324020819026719246443385844477385088676696326300446558031780197028589297378605095939742913766764573396746118478089429324031259540383687604 [0x96dbfa404a8b5d59c53dc701f0deb40127d3bc74cd60b35fb77d6d404987ee250a1bfca32a81027abe24d7ed739f20444a245791c84297aede08fd0c7e1963b4]) AES key at state StCreatorRootKey for Sealing Aes
  UVM_INFO @ 453679581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

29.keymgr_stress_all_with_rand_reset.100021888272631581770740855744084577575290175312940608560449716424857625036864
Line 371, in log /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 305875281 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (2775966213550243917974544322059131718543192067906046058652046797072198349138781303232275282530060295937393550537072926800895683767942224937285029202198167348246907957331970384747543054864401496566574563608330522306204521184764389497331270270917924615534388937920549749238697266862736197575264946341808157607750255803025365762036357254899449377529 [0xb9dfcbc27369fd1405b1ec23be41112c2053a1519c859e778619709a618af82000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f5073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9] vs 28707857971979780283949451429872074208980287204051622235734115982644347508544038432438735739233499335449046654381132930015116958969792161717275748719395248185603086541129104867344383339236530842884215401219100936816914947664807043711027201304755985588092243850192162071789734095484961712470399241987583313679771424507842172953791784832148902687481 [0x7823b4fd11113160934cc9b494d004dd655ff8bfd35ba057f2e6dfd86fccc9b8000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f5073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9]) cdi_type: Attestation
  
   HardwareRevisionSecret act: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9, exp: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9
   RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e