KEYMGR Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	28.660s	3.592ms	49	50	98.00
V1	random	keymgr_random	1.151m	2.153ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.810s	210.708us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.920s	95.548us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	21.540s	2.653ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	12.010s	470.383us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.730s	147.821us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.920s	95.548us	20	20	100.00
		keymgr_csr_aliasing	12.010s	470.383us	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	2.277m	2.571ms	50	50	100.00
V2	sideload	keymgr_sideload	55.920s	5.899ms	50	50	100.00
		keymgr_sideload_kmac	40.590s	13.141ms	50	50	100.00
		keymgr_sideload_aes	29.090s	1.086ms	50	50	100.00
		keymgr_sideload_otbn	1.050m	1.832ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	40.890s	1.166ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	8.370s	221.527us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	19.010s	841.490us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	57.910s	3.308ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	41.320s	7.685ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	14.910s	1.022ms	50	50	100.00
V2	stress_all	keymgr_stress_all	5.253m	22.793ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.240s	94.449us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.540s	31.076us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	7.500s	327.390us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	7.500s	327.390us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.810s	210.708us	5	5	100.00
		keymgr_csr_rw	1.920s	95.548us	20	20	100.00
		keymgr_csr_aliasing	12.010s	470.383us	5	5	100.00
		keymgr_same_csr_outstanding	5.510s	118.476us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.810s	210.708us	5	5	100.00
		keymgr_csr_rw	1.920s	95.548us	20	20	100.00
		keymgr_csr_aliasing	12.010s	470.383us	5	5	100.00
		keymgr_same_csr_outstanding	5.510s	118.476us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	sec_cm_additional_check	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
		keymgr_tl_intg_err	12.490s	411.261us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.270s	217.213us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.270s	217.213us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.270s	217.213us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.270s	217.213us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	18.420s	1.602ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	12.490s	411.261us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.270s	217.213us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.277m	2.571ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.151m	2.153ms	50	50	100.00
		keymgr_csr_rw	1.920s	95.548us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.151m	2.153ms	50	50	100.00
		keymgr_csr_rw	1.920s	95.548us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.151m	2.153ms	50	50	100.00
		keymgr_csr_rw	1.920s	95.548us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.370s	221.527us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	41.320s	7.685ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	41.320s	7.685ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.151m	2.153ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	27.920s	4.134ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	10.370s	2.337ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.370s	221.527us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	10.370s	2.337ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	10.370s	2.337ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	10.370s	2.337ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	18.810s	4.500ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	10.370s	2.337ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	31.360s	2.611ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1087	1110	97.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.04	98.07	98.46	100.00	99.02	98.63	91.27

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test keymgr_stress_all_with_rand_reset has 19 failures.

    • 1.keymgr_stress_all_with_rand_reset.1878663672778836532253935486674341166992461155777266167475572527248198756213
      Line 288, in log /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 148528581 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 148528581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.keymgr_stress_all_with_rand_reset.68494520124856437458092744727691502958665182325251860580407871342592811375641
      Line 295, in log /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 451994926 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 451994926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_stress_all has 1 failures.

    • 13.keymgr_stress_all.44634967400633848580230239613815775392332695134963850870708687618947499633987
      Line 1662, in log /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 1385578744 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 1385578744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_smoke has 1 failures.

    • 36.keymgr_smoke.30424052416116206277338330019455819354940302592665625958390501079764455180442
      Line 111, in log /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_smoke/latest/run.log

        UVM_ERROR @  34994961 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  34994961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:

  • Test keymgr_lc_disable has 1 failures.

    • 11.keymgr_lc_disable.79069011717033395921302307442282625580056622019261603369373125622992601315872
      Line 345, in log /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_lc_disable/latest/run.log

        UVM_ERROR @ 483002499 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_1
        UVM_INFO @ 483002499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 37.keymgr_stress_all.53839021789146557236561412039691496305026547581226221958492478704844263524185
      Line 274, in log /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_stress_all/latest/run.log

        UVM_ERROR @  57314818 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (2 [0x2] vs 3 [0x3])
        UVM_INFO @  57314818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.08.28_06.55.44
• 2024.08.26_02.16.57
• 2024.08.24_20.02.58
• 2024.08.22_14.04.34
• 2024.08.20_07.48.38
• 2024.08.19_08.02.31