e3fb01b5e
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | kmac_smoke | 1.750m | 30.990ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | kmac_csr_hw_reset | 1.160s | 27.404us | 5 | 5 | 100.00 |
V1 | csr_rw | kmac_csr_rw | 1.280s | 36.072us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | kmac_csr_bit_bash | 21.160s | 1.995ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | kmac_csr_aliasing | 9.010s | 610.856us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.280s | 354.533us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.280s | 36.072us | 20 | 20 | 100.00 |
kmac_csr_aliasing | 9.010s | 610.856us | 5 | 5 | 100.00 | ||
V1 | mem_walk | kmac_mem_walk | 0.770s | 16.972us | 5 | 5 | 100.00 |
V1 | mem_partial_access | kmac_mem_partial_access | 1.550s | 133.586us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | long_msg_and_output | kmac_long_msg_and_output | 58.091m | 434.074ms | 47 | 50 | 94.00 |
V2 | burst_write | kmac_burst_write | 27.674m | 64.487ms | 47 | 50 | 94.00 |
V2 | test_vectors | kmac_test_vectors_sha3_224 | 44.791m | 1.046s | 50 | 50 | 100.00 |
kmac_test_vectors_sha3_256 | 43.317m | 153.148ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_384 | 35.488m | 646.951ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_512 | 25.278m | 178.022ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_128 | 1.851h | 523.612ms | 47 | 50 | 94.00 | ||
kmac_test_vectors_shake_256 | 1.690h | 2.010s | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac | 9.020s | 1.036ms | 49 | 50 | 98.00 | ||
kmac_test_vectors_kmac_xof | 7.020s | 415.564us | 50 | 50 | 100.00 | ||
V2 | sideload | kmac_sideload | 8.898m | 21.994ms | 50 | 50 | 100.00 |
V2 | app | kmac_app | 6.889m | 12.642ms | 50 | 50 | 100.00 |
V2 | app_with_partial_data | kmac_app_with_partial_data | 5.820m | 63.187ms | 10 | 10 | 100.00 |
V2 | entropy_refresh | kmac_entropy_refresh | 6.713m | 18.225ms | 49 | 50 | 98.00 |
V2 | error | kmac_error | 8.725m | 5.768ms | 48 | 50 | 96.00 |
V2 | key_error | kmac_key_error | 8.470s | 10.409ms | 50 | 50 | 100.00 |
V2 | edn_timeout_error | kmac_edn_timeout_error | 42.810s | 6.861ms | 20 | 20 | 100.00 |
V2 | entropy_mode_error | kmac_entropy_mode_error | 46.810s | 5.939ms | 20 | 20 | 100.00 |
V2 | entropy_ready_error | kmac_entropy_ready_error | 1.554m | 74.653ms | 10 | 10 | 100.00 |
V2 | lc_escalation | kmac_lc_escalation | 50.160s | 5.909ms | 50 | 50 | 100.00 |
V2 | stress_all | kmac_stress_all | 42.866m | 131.741ms | 47 | 50 | 94.00 |
V2 | intr_test | kmac_intr_test | 0.890s | 20.827us | 50 | 50 | 100.00 |
V2 | alert_test | kmac_alert_test | 0.920s | 62.340us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.210s | 112.449us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | kmac_tl_errors | 3.210s | 112.449us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.160s | 27.404us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.280s | 36.072us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 9.010s | 610.856us | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.990s | 146.890us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.160s | 27.404us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.280s | 36.072us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 9.010s | 610.856us | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.990s | 146.890us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1034 | 1050 | 98.48 | |||
V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.160s | 99.875us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.160s | 99.875us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.160s | 99.875us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.160s | 99.875us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 6.290s | 556.221us | 20 | 20 | 100.00 |
V2S | tl_intg_err | kmac_sec_cm | 2.183m | 7.986ms | 5 | 5 | 100.00 |
kmac_tl_intg_err | 5.480s | 517.996us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.480s | 517.996us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 50.160s | 5.909ms | 50 | 50 | 100.00 |
V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.750m | 30.990ms | 50 | 50 | 100.00 |
V2S | sec_cm_key_sideload | kmac_sideload | 8.898m | 21.994ms | 50 | 50 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.160s | 99.875us | 20 | 20 | 100.00 |
V2S | sec_cm_fsm_sparse | kmac_sec_cm | 2.183m | 7.986ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | kmac_sec_cm | 2.183m | 7.986ms | 5 | 5 | 100.00 |
V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 2.183m | 7.986ms | 5 | 5 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.750m | 30.990ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 50.160s | 5.909ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 2.183m | 7.986ms | 5 | 5 | 100.00 |
V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 7.237m | 32.386ms | 10 | 10 | 100.00 |
V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.750m | 30.990ms | 50 | 50 | 100.00 |
V2S | TOTAL | 75 | 75 | 100.00 | |||
V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.158h | 126.665ms | 34 | 50 | 68.00 |
V3 | TOTAL | 34 | 50 | 68.00 | |||
TOTAL | 1258 | 1290 | 97.52 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 25 | 25 | 18 | 72.00 |
V2S | 5 | 5 | 5 | 100.00 |
V3 | 2 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.06 | 98.40 | 93.36 | 99.93 | 94.55 | 96.03 | 98.87 | 98.31 |
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code
has 14 failures:
10.kmac_stress_all_with_rand_reset.339164871
Line 697, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 56401818453 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
UVM_INFO @ 56401818453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.kmac_stress_all_with_rand_reset.716651918
Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43861935 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
UVM_INFO @ 43861935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 4 failures:
8.kmac_burst_write.3338163868
Line 397, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.kmac_burst_write.4165958625
Line 367, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
15.kmac_entropy_refresh.1680685584
Line 375, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 4 failures:
9.kmac_long_msg_and_output.314411757
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest/run.log
Job ID: smart:594bc19b-4088-41ae-a083-c73dd0edb203
37.kmac_long_msg_and_output.1293586759
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest/run.log
Job ID: smart:0b628d59-aad9-4ef6-b851-a065ec9b4c73
... and 1 more failures.
31.kmac_test_vectors_shake_128.549964785
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_shake_128/latest/run.log
Job ID: smart:b5bfe784-f67b-4ae5-8d38-411d8a2c1065
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
has 3 failures:
Test kmac_test_vectors_shake_128 has 2 failures.
2.kmac_test_vectors_shake_128.3927691610
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
UVM_ERROR @ 53157627 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 53157627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.kmac_test_vectors_shake_128.4123093741
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_shake_128/latest/run.log
UVM_ERROR @ 289108590 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 289108590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_kmac has 1 failures.
43.kmac_test_vectors_kmac.3473525893
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_test_vectors_kmac/latest/run.log
UVM_ERROR @ 36872685 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 36872685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request
has 3 failures:
Test kmac_stress_all has 1 failures.
7.kmac_stress_all.3082944652
Line 538, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all/latest/run.log
UVM_FATAL @ 55306465259 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 55306465259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all_with_rand_reset has 1 failures.
40.kmac_stress_all_with_rand_reset.2310508944
Line 409, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 12058814903 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 12058814903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 1 failures.
48.kmac_error.218508285
Line 371, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_error/latest/run.log
UVM_FATAL @ 10086463444 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10086463444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]
has 2 failures:
Test kmac_stress_all has 1 failures.
33.kmac_stress_all.4195322507
Line 438, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_stress_all/latest/run.log
UVM_FATAL @ 188901957869 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (28 [0x1c] vs 131 [0x83]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 188901957869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 1 failures.
41.kmac_error.3820115255
Line 415, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_error/latest/run.log
UVM_FATAL @ 12587364740 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (151 [0x97] vs 87 [0x57]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 12587364740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'rand_valid_o'
has 1 failures:
1.kmac_stress_all.3149484092
Line 266, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all/latest/run.log
Offending 'rand_valid_o'
UVM_ERROR @ 5363393367 ps: (kmac_entropy.sv:503) [ASSERT FAILED] ConsumeNotAseertWhenNotReady_M
UVM_INFO @ 5363393367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*]
has 1 failures:
25.kmac_stress_all_with_rand_reset.2433475818
Line 657, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 30483647601 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (229 [0xe5] vs 162 [0xa2]) Mismatch between exp_digest[0] and act_digest[0]
UVM_INFO @ 30483647601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---