042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.678m | 22.441ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.200s | 53.729us | 3 | 5 | 60.00 |
| V1 | csr_rw | kmac_csr_rw | 1.210s | 27.651us | 13 | 20 | 65.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 23.180s | 1.621ms | 3 | 5 | 60.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 12.140s | 5.462ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.040s | 116.613us | 17 | 20 | 85.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.210s | 27.651us | 13 | 20 | 65.00 |
| kmac_csr_aliasing | 12.140s | 5.462ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.740s | 41.664us | 3 | 5 | 60.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.420s | 67.057us | 4 | 5 | 80.00 |
| V1 | TOTAL | 98 | 115 | 85.22 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 55.562m | 1.285s | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 25.657m | 56.776ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 42.535m | 392.215ms | 50 | 50 | 100.00 |
| kmac_test_vectors_sha3_256 | 40.791m | 1.041s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 34.569m | 785.649ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 23.974m | 287.447ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.742h | 1.624s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_256 | 1.508h | 1.041s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac | 7.570s | 4.412ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 7.790s | 946.463us | 50 | 50 | 100.00 | ||
| V2 | sideload | kmac_sideload | 9.390m | 91.476ms | 47 | 50 | 94.00 |
| V2 | app | kmac_app | 6.875m | 18.536ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 6.325m | 39.301ms | 9 | 10 | 90.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 8.006m | 92.453ms | 48 | 50 | 96.00 |
| V2 | error | kmac_error | 8.646m | 161.212ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 8.340s | 2.654ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 47.730s | 27.300ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 46.790s | 2.113ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.200m | 17.591ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 53.030s | 893.495us | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 47.397m | 32.714ms | 47 | 50 | 94.00 |
| V2 | intr_test | kmac_intr_test | 0.870s | 19.463us | 38 | 50 | 76.00 |
| V2 | alert_test | kmac_alert_test | 0.920s | 102.661us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.350s | 129.657us | 18 | 20 | 90.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.350s | 129.657us | 18 | 20 | 90.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.200s | 53.729us | 3 | 5 | 60.00 |
| kmac_csr_rw | 1.210s | 27.651us | 13 | 20 | 65.00 | ||
| kmac_csr_aliasing | 12.140s | 5.462ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.680s | 141.589us | 13 | 20 | 65.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.200s | 53.729us | 3 | 5 | 60.00 |
| kmac_csr_rw | 1.210s | 27.651us | 13 | 20 | 65.00 | ||
| kmac_csr_aliasing | 12.140s | 5.462ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.680s | 141.589us | 13 | 20 | 65.00 | ||
| V2 | TOTAL | 1020 | 1050 | 97.14 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.370s | 64.220us | 14 | 20 | 70.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.370s | 64.220us | 14 | 20 | 70.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.370s | 64.220us | 14 | 20 | 70.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.370s | 64.220us | 14 | 20 | 70.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 2.590s | 106.440us | 13 | 20 | 65.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.934m | 36.143ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.250s | 428.361us | 17 | 20 | 85.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.250s | 428.361us | 17 | 20 | 85.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 53.030s | 893.495us | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.678m | 22.441ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 9.390m | 91.476ms | 47 | 50 | 94.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.370s | 64.220us | 14 | 20 | 70.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.934m | 36.143ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.934m | 36.143ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.934m | 36.143ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.678m | 22.441ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 53.030s | 893.495us | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.934m | 36.143ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 6.253m | 121.631ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.678m | 22.441ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 59 | 75 | 78.67 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 53.613m | 1.293s | 34 | 50 | 68.00 |
| V3 | TOTAL | 34 | 50 | 68.00 | |||
| TOTAL | 1211 | 1290 | 93.88 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 2 | 25.00 |
| V2 | 25 | 25 | 18 | 72.00 |
| V2S | 5 | 5 | 2 | 40.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.97 | 98.38 | 93.15 | 99.93 | 94.55 | 96.04 | 98.58 | 98.17 |
Exit reason: Error: User command failed Job returned non-zero exit code has 52 failures:
Test kmac_intr_test has 12 failures.
0.kmac_intr_test.47587467723973137565170805592840378182433065605385915101804687814304238963077
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_intr_test/latest/run.log
[make]: simulate
cd /workspace/0.kmac_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372096901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1372096901 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
4.kmac_intr_test.36400535864489394857492026609036637450141381426548555163186094391231036371082
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_intr_test/latest/run.log
[make]: simulate
cd /workspace/4.kmac_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640162954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2640162954 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 10 more failures.
Test kmac_csr_bit_bash has 2 failures.
0.kmac_csr_bit_bash.109512499049922111137834547816004371168165155172065282869186007668091473564886
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/0.kmac_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110119638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1110119638 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.kmac_csr_bit_bash.61765809908881854834507090080822701450756447067630100235381344713845133684725
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/1.kmac_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165190645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2165190645 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test kmac_shadow_reg_errors has 6 failures.
1.kmac_shadow_reg_errors.67090632974367648809066808456426071307142469100152444077460024580013163480024
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log
[make]: simulate
cd /workspace/1.kmac_shadow_reg_errors/latest && /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50267096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.50267096 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.kmac_shadow_reg_errors.8555440403387269431303871642651509050414573837334056482449889395931605023198
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest/run.log
[make]: simulate
cd /workspace/3.kmac_shadow_reg_errors/latest && /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530758110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.530758110 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 4 more failures.
Test kmac_mem_partial_access has 1 failures.
1.kmac_mem_partial_access.90113985102707818855216136510607761314505552010530018734587974556418005957869
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest/run.log
[make]: simulate
cd /workspace/1.kmac_mem_partial_access/latest && /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474198765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.1474198765 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test kmac_mem_walk has 2 failures.
2.kmac_mem_walk.30961952694293933221726178258053084861849125287737515226045563169830559773745
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_mem_walk/latest/run.log
[make]: simulate
cd /workspace/2.kmac_mem_walk/latest && /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744087601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2744087601 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.kmac_mem_walk.56140479118047668160955307816241596635707276649756749653204547820039966283410
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_mem_walk/latest/run.log
[make]: simulate
cd /workspace/3.kmac_mem_walk/latest && /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836228754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.836228754 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 7 more tests.
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 12 failures:
0.kmac_stress_all_with_rand_reset.93152959050368815997520519257103554001265809890963113578996049121809618615495
Line 284, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27818126 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
UVM_INFO @ 27818126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.kmac_stress_all_with_rand_reset.58350899710689606520942532634514462324305052335719101188594593194231778077269
Line 1071, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 196508735357 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
UVM_INFO @ 196508735357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
4.kmac_sideload.58535789284960707324559038820654991802218212207215777851587559663231881856524
Line 379, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_sideload/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.kmac_sideload.40446070036363315909592978091162161127280678864328174496699681112094762890451
Line 383, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_sideload/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
45.kmac_entropy_refresh.82804131717767566090109441744048905108836305485480564896162363986012347527606
Line 376, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:
Test kmac_app_with_partial_data has 1 failures.
6.kmac_app_with_partial_data.115353513539449909616395454450946280279907313624659694922799383385642968470757
Line 375, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest/run.log
UVM_FATAL @ 24174490923 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (243 [0xf3] vs 22 [0x16]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 24174490923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
10.kmac_entropy_refresh.39487233539212806085672759012745410481226346554672427078177379071041657342569
Line 407, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 26054302479 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (17 [0x11] vs 56 [0x38]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 26054302479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
36.kmac_stress_all.71122646698750312231799929955342484868138028976867472111105907833373425849167
Line 468, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_stress_all/latest/run.log
UVM_FATAL @ 11109347962 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (151 [0x97] vs 11 [0xb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 11109347962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
Test kmac_stress_all has 1 failures.
13.kmac_stress_all.67396421397539141222601740426309980010578107155390651136348043365513295184597
Line 368, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all/latest/run.log
UVM_FATAL @ 20597881201 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 20597881201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all_with_rand_reset has 2 failures.
17.kmac_stress_all_with_rand_reset.36453432640532750606301508986735022487593442951713483858801726081065247896610
Line 493, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 26262742182 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 26262742182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.kmac_stress_all_with_rand_reset.95497493790413726220659010586684090906262713646812623368803162706587388099876
Line 663, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 111920929445 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 111920929445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_masked-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
Test kmac_tl_intg_err has 1 failures.
10.kmac_tl_intg_err.31466380832058494711155616298351404763116632736287888864991687427172806116498
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest/run.log
Job ID: smart:bdf60609-9497-4698-9dce-cf54008c62a2
Test kmac_same_csr_outstanding has 1 failures.
15.kmac_same_csr_outstanding.23316107257245581344164716588527104557560127261598989443775212660702271325391
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest/run.log
Job ID: smart:0d03c150-5b53-4f1a-927a-7c49e87cf6eb
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
1.kmac_stress_all.65595405591360287467422113322941673418630525308692851853252164582560227115553
Line 278, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all/latest/run.log
UVM_ERROR @ 54712197 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 54712197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
22.kmac_stress_all_with_rand_reset.91911665716739704664563557511606343115686100637404468193533184789821496267186
Line 876, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 101617630133 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (23 [0x17] vs 192 [0xc0]) Mismatch between exp_digest[0] and act_digest[0]
UVM_INFO @ 101617630133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
47.kmac_stress_all_with_rand_reset.6558639788846079059467470218829558687411628806187527819863617755375450432016
Line 284, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 329010668 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (59 [0x3b] vs 163 [0xa3]) Mismatch between exp_digest[0] and act_digest[0]
UVM_INFO @ 329010668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---