KMAC/MASKED Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.867m 19.969ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.320s 35.909us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.360s 35.854us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 24.350s 11.506ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 10.110s 2.190ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 5.710s 874.080us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.360s 35.854us 20 20 100.00
kmac_csr_aliasing 10.110s 2.190ms 5 5 100.00
V1 mem_walk kmac_mem_walk 0.830s 55.181us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.440s 229.311us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 55.217m 495.202ms 49 50 98.00
V2 burst_write kmac_burst_write 27.554m 13.393ms 44 50 88.00
V2 test_vectors kmac_test_vectors_sha3_224 52.900m 1.954s 50 50 100.00
kmac_test_vectors_sha3_256 42.493m 380.154ms 50 50 100.00
kmac_test_vectors_sha3_384 34.942m 484.176ms 50 50 100.00
kmac_test_vectors_sha3_512 24.228m 52.519ms 50 50 100.00
kmac_test_vectors_shake_128 1.873h 280.212ms 50 50 100.00
kmac_test_vectors_shake_256 1.696h 2.008s 50 50 100.00
kmac_test_vectors_kmac 7.460s 251.093us 50 50 100.00
kmac_test_vectors_kmac_xof 7.850s 1.155ms 50 50 100.00
V2 sideload kmac_sideload 9.572m 22.122ms 50 50 100.00
V2 app kmac_app 7.319m 29.369ms 48 50 96.00
V2 app_with_partial_data kmac_app_with_partial_data 6.359m 73.468ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 8.068m 82.906ms 49 50 98.00
V2 error kmac_error 9.654m 21.998ms 49 50 98.00
V2 key_error kmac_key_error 7.130s 1.203ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 51.820s 2.367ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 51.830s 2.088ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.353m 15.189ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 39.050s 1.746ms 50 50 100.00
V2 stress_all kmac_stress_all 1.106h 133.167ms 46 50 92.00
V2 intr_test kmac_intr_test 0.920s 55.566us 50 50 100.00
V2 alert_test kmac_alert_test 0.910s 85.953us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 4.000s 2.420ms 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 4.000s 2.420ms 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.320s 35.909us 5 5 100.00
kmac_csr_rw 1.360s 35.854us 20 20 100.00
kmac_csr_aliasing 10.110s 2.190ms 5 5 100.00
kmac_same_csr_outstanding 3.260s 464.840us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.320s 35.909us 5 5 100.00
kmac_csr_rw 1.360s 35.854us 20 20 100.00
kmac_csr_aliasing 10.110s 2.190ms 5 5 100.00
kmac_same_csr_outstanding 3.260s 464.840us 20 20 100.00
V2 TOTAL 1035 1050 98.57
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.710s 100.799us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.710s 100.799us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.710s 100.799us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.710s 100.799us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.360s 290.717us 19 20 95.00
V2S tl_intg_err kmac_sec_cm 1.863m 7.359ms 5 5 100.00
kmac_tl_intg_err 5.260s 1.609ms 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.260s 1.609ms 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 39.050s 1.746ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.867m 19.969ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 9.572m 22.122ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.710s 100.799us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.863m 7.359ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.863m 7.359ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.863m 7.359ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.867m 19.969ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 39.050s 1.746ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.863m 7.359ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 8.552m 42.463ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.867m 19.969ms 50 50 100.00
V2S TOTAL 74 75 98.67
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 1.003h 1.591s 12 50 24.00
V3 TOTAL 12 50 24.00
TOTAL 1236 1290 95.81

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 19 76.00
V2S 5 5 4 80.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.26 98.38 93.11 99.93 96.36 95.98 98.89 98.17

Failure Buckets

Past Results