8faf04697a
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | kmac_smoke | 1.867m | 19.969ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | kmac_csr_hw_reset | 1.320s | 35.909us | 5 | 5 | 100.00 |
V1 | csr_rw | kmac_csr_rw | 1.360s | 35.854us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | kmac_csr_bit_bash | 24.350s | 11.506ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | kmac_csr_aliasing | 10.110s | 2.190ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 5.710s | 874.080us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.360s | 35.854us | 20 | 20 | 100.00 |
kmac_csr_aliasing | 10.110s | 2.190ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | kmac_mem_walk | 0.830s | 55.181us | 5 | 5 | 100.00 |
V1 | mem_partial_access | kmac_mem_partial_access | 1.440s | 229.311us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | long_msg_and_output | kmac_long_msg_and_output | 55.217m | 495.202ms | 49 | 50 | 98.00 |
V2 | burst_write | kmac_burst_write | 27.554m | 13.393ms | 44 | 50 | 88.00 |
V2 | test_vectors | kmac_test_vectors_sha3_224 | 52.900m | 1.954s | 50 | 50 | 100.00 |
kmac_test_vectors_sha3_256 | 42.493m | 380.154ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_384 | 34.942m | 484.176ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_512 | 24.228m | 52.519ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_128 | 1.873h | 280.212ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_256 | 1.696h | 2.008s | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac | 7.460s | 251.093us | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac_xof | 7.850s | 1.155ms | 50 | 50 | 100.00 | ||
V2 | sideload | kmac_sideload | 9.572m | 22.122ms | 50 | 50 | 100.00 |
V2 | app | kmac_app | 7.319m | 29.369ms | 48 | 50 | 96.00 |
V2 | app_with_partial_data | kmac_app_with_partial_data | 6.359m | 73.468ms | 10 | 10 | 100.00 |
V2 | entropy_refresh | kmac_entropy_refresh | 8.068m | 82.906ms | 49 | 50 | 98.00 |
V2 | error | kmac_error | 9.654m | 21.998ms | 49 | 50 | 98.00 |
V2 | key_error | kmac_key_error | 7.130s | 1.203ms | 50 | 50 | 100.00 |
V2 | edn_timeout_error | kmac_edn_timeout_error | 51.820s | 2.367ms | 20 | 20 | 100.00 |
V2 | entropy_mode_error | kmac_entropy_mode_error | 51.830s | 2.088ms | 20 | 20 | 100.00 |
V2 | entropy_ready_error | kmac_entropy_ready_error | 1.353m | 15.189ms | 10 | 10 | 100.00 |
V2 | lc_escalation | kmac_lc_escalation | 39.050s | 1.746ms | 50 | 50 | 100.00 |
V2 | stress_all | kmac_stress_all | 1.106h | 133.167ms | 46 | 50 | 92.00 |
V2 | intr_test | kmac_intr_test | 0.920s | 55.566us | 50 | 50 | 100.00 |
V2 | alert_test | kmac_alert_test | 0.910s | 85.953us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.000s | 2.420ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | kmac_tl_errors | 4.000s | 2.420ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.320s | 35.909us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.360s | 35.854us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 10.110s | 2.190ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 3.260s | 464.840us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.320s | 35.909us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.360s | 35.854us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 10.110s | 2.190ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 3.260s | 464.840us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1035 | 1050 | 98.57 | |||
V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.710s | 100.799us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.710s | 100.799us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.710s | 100.799us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.710s | 100.799us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.360s | 290.717us | 19 | 20 | 95.00 |
V2S | tl_intg_err | kmac_sec_cm | 1.863m | 7.359ms | 5 | 5 | 100.00 |
kmac_tl_intg_err | 5.260s | 1.609ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.260s | 1.609ms | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 39.050s | 1.746ms | 50 | 50 | 100.00 |
V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.867m | 19.969ms | 50 | 50 | 100.00 |
V2S | sec_cm_key_sideload | kmac_sideload | 9.572m | 22.122ms | 50 | 50 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.710s | 100.799us | 20 | 20 | 100.00 |
V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.863m | 7.359ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.863m | 7.359ms | 5 | 5 | 100.00 |
V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.863m | 7.359ms | 5 | 5 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.867m | 19.969ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 39.050s | 1.746ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.863m | 7.359ms | 5 | 5 | 100.00 |
V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 8.552m | 42.463ms | 10 | 10 | 100.00 |
V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.867m | 19.969ms | 50 | 50 | 100.00 |
V2S | TOTAL | 74 | 75 | 98.67 | |||
V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.003h | 1.591s | 12 | 50 | 24.00 |
V3 | TOTAL | 12 | 50 | 24.00 | |||
TOTAL | 1236 | 1290 | 95.81 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 25 | 25 | 19 | 76.00 |
V2S | 5 | 5 | 4 | 80.00 |
V3 | 2 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.26 | 98.38 | 93.11 | 99.93 | 96.36 | 95.98 | 98.89 | 98.17 |
UVM_ERROR (cip_base_vseq.sv:756) [kmac_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
has 29 failures:
0.kmac_stress_all_with_rand_reset.78474629339647889513846835967229899567630918163210932215996617814662011230290
Line 395, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27171432509 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 27171432509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.kmac_stress_all_with_rand_reset.10459962108591023340491983863483995294570198934947314820895350768940108104822
Line 398, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23735299884 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 23735299884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 7 failures:
Test kmac_error has 1 failures.
2.kmac_error.23769496294088133781696295631719373926682215196813969124874366464472840823760
Line 790, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_burst_write has 6 failures.
11.kmac_burst_write.111866252200045563649300267046404008546642427278391258910293136650562459896698
Line 826, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.kmac_burst_write.104256670601800505908904272570772998393393819546052617939717874436786421954856
Line 1099, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code
has 6 failures:
4.kmac_stress_all_with_rand_reset.84695375017057479195953112220737219610375106319508216499522793991619736810185
Line 876, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 86472992376 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
UVM_INFO @ 86472992376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_stress_all_with_rand_reset.70459924933909024742466246643483433321372956475381308863024104646502345697988
Line 285, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 74201650 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
UVM_INFO @ 74201650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]
has 5 failures:
Test kmac_app has 2 failures.
7.kmac_app.108171811591878115864954858378464824327188345836976567613405593657625493876470
Line 430, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_app/latest/run.log
UVM_FATAL @ 10099522557 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (255 [0xff] vs 18 [0x12]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 10099522557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.kmac_app.22073653385679711042296054379376163438428911434614576856799419842668297117084
Line 490, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_app/latest/run.log
UVM_FATAL @ 15387266002 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (202 [0xca] vs 61 [0x3d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 15387266002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
9.kmac_stress_all.37300881080074233942116420639556510100376691163246554864087792812753665631812
Line 1516, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all/latest/run.log
UVM_FATAL @ 213496654770 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (97 [0x61] vs 92 [0x5c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 213496654770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
25.kmac_entropy_refresh.11535895685998828201522453508570551307423416513872570317928858500759536111104
Line 334, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 1759999357 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (17 [0x11] vs 245 [0xf5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 1759999357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all_with_rand_reset has 1 failures.
49.kmac_stress_all_with_rand_reset.70504197629322777265471613071059551054970277483507462395052716464094188378573
Line 571, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 8209617446 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (67 [0x43] vs 120 [0x78]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 8209617446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request
has 3 failures:
Test kmac_stress_all has 2 failures.
1.kmac_stress_all.98049243287443647303770077908395456722227874734809746521876946612981873057520
Line 965, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all/latest/run.log
UVM_FATAL @ 140092261240 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 140092261240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.kmac_stress_all.40727367182799638855665920728798469033561961430435312648674865744404207332339
Line 1059, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all/latest/run.log
UVM_FATAL @ 30924081517 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 30924081517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all_with_rand_reset has 1 failures.
21.kmac_stress_all_with_rand_reset.110612880882337714969812226838235868814382994306616824707966398950789278511696
Line 1028, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 317268405746 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 317268405746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: *
has 1 failures:
18.kmac_shadow_reg_errors_with_csr_rw.81203113466339381253338088793911218420630534756247053462008545227178358117269
Line 280, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 44227487 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (68385251 [0x41379e3] vs 0 [0x0]) Regname: kmac_reg_block.prefix_2 reset value: 0x0
UVM_INFO @ 44227487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
has 1 failures:
27.kmac_stress_all.53201272781788141319935263333481214014856996718439322383699985332108586614285
Line 312, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all/latest/run.log
UVM_ERROR @ 410547852 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 410547852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:714) [kmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
has 1 failures:
28.kmac_stress_all_with_rand_reset.10363032936368770577614204917960247225671517282989535976951752283372972146098
Line 483, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9145264191 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 9145264191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 1 failures:
49.kmac_long_msg_and_output.43344863182421758102687553478526444658103334400966455984428539823224485686156
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest/run.log
Job ID: smart:c2e097ac-1aa9-4f1b-bc19-54260cd4361e