KMAC/MASKED Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.667m 3.592ms 48 50 96.00
V1 csr_hw_reset kmac_csr_hw_reset 1.190s 56.166us 4 5 80.00
V1 csr_rw kmac_csr_rw 1.400s 427.247us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 24.780s 3.499ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 11.280s 1.799ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.040s 99.670us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.400s 427.247us 20 20 100.00
kmac_csr_aliasing 11.280s 1.799ms 5 5 100.00
V1 mem_walk kmac_mem_walk 0.830s 27.830us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.660s 540.701us 5 5 100.00
V1 TOTAL 112 115 97.39
V2 long_msg_and_output kmac_long_msg_and_output 55.247m 85.937ms 49 50 98.00
V2 burst_write kmac_burst_write 27.818m 15.229ms 48 50 96.00
V2 test_vectors kmac_test_vectors_sha3_224 46.812m 520.419ms 49 50 98.00
kmac_test_vectors_sha3_256 43.645m 417.129ms 47 50 94.00
kmac_test_vectors_sha3_384 33.980m 154.939ms 47 50 94.00
kmac_test_vectors_sha3_512 26.122m 617.906ms 49 50 98.00
kmac_test_vectors_shake_128 1.890h 1.440s 48 50 96.00
kmac_test_vectors_shake_256 1.618h 1.356s 45 50 90.00
kmac_test_vectors_kmac 7.570s 399.770us 50 50 100.00
kmac_test_vectors_kmac_xof 7.430s 1.347ms 48 50 96.00
V2 sideload kmac_sideload 9.808m 45.604ms 49 50 98.00
V2 app kmac_app 7.485m 14.936ms 47 50 94.00
V2 app_with_partial_data kmac_app_with_partial_data 7.317m 60.698ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 7.156m 15.091ms 47 50 94.00
V2 error kmac_error 9.742m 19.090ms 48 50 96.00
V2 key_error kmac_key_error 9.970s 11.190ms 48 50 96.00
V2 edn_timeout_error kmac_edn_timeout_error 47.810s 3.851ms 18 20 90.00
V2 entropy_mode_error kmac_entropy_mode_error 32.860s 2.420ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.525m 30.967ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 44.960s 2.922ms 49 50 98.00
V2 stress_all kmac_stress_all 49.959m 36.830ms 47 50 94.00
V2 intr_test kmac_intr_test 0.940s 24.654us 50 50 100.00
V2 alert_test kmac_alert_test 0.990s 33.857us 49 50 98.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.420s 121.684us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.420s 121.684us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.190s 56.166us 4 5 80.00
kmac_csr_rw 1.400s 427.247us 20 20 100.00
kmac_csr_aliasing 11.280s 1.799ms 5 5 100.00
kmac_same_csr_outstanding 3.120s 256.289us 19 20 95.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.190s 56.166us 4 5 80.00
kmac_csr_rw 1.400s 427.247us 20 20 100.00
kmac_csr_aliasing 11.280s 1.799ms 5 5 100.00
kmac_same_csr_outstanding 3.120s 256.289us 19 20 95.00
V2 TOTAL 1011 1050 96.29
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.560s 101.490us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.560s 101.490us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.560s 101.490us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.560s 101.490us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.690s 1.069ms 19 20 95.00
V2S tl_intg_err kmac_sec_cm 1.973m 7.865ms 5 5 100.00
kmac_tl_intg_err 6.740s 1.350ms 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 6.740s 1.350ms 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 44.960s 2.922ms 49 50 98.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.667m 3.592ms 48 50 96.00
V2S sec_cm_key_sideload kmac_sideload 9.808m 45.604ms 49 50 98.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.560s 101.490us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.973m 7.865ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.973m 7.865ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.973m 7.865ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.667m 3.592ms 48 50 96.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 44.960s 2.922ms 49 50 98.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.973m 7.865ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 7.575m 55.816ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.667m 3.592ms 48 50 96.00
V2S TOTAL 74 75 98.67
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 42.998m 261.363ms 34 50 68.00
V3 TOTAL 34 50 68.00
TOTAL 1231 1290 95.43

Testplan Progress

Items Total Written Passing Progress
V1 8 8 6 75.00
V2 25 25 6 24.00
V2S 5 5 4 80.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.03 98.38 93.14 99.93 94.55 96.04 98.89 98.31

Failure Buckets

Past Results