17d5a97c3b
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | kmac_smoke | 1.667m | 3.592ms | 48 | 50 | 96.00 |
V1 | csr_hw_reset | kmac_csr_hw_reset | 1.190s | 56.166us | 4 | 5 | 80.00 |
V1 | csr_rw | kmac_csr_rw | 1.400s | 427.247us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | kmac_csr_bit_bash | 24.780s | 3.499ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | kmac_csr_aliasing | 11.280s | 1.799ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.040s | 99.670us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.400s | 427.247us | 20 | 20 | 100.00 |
kmac_csr_aliasing | 11.280s | 1.799ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | kmac_mem_walk | 0.830s | 27.830us | 5 | 5 | 100.00 |
V1 | mem_partial_access | kmac_mem_partial_access | 1.660s | 540.701us | 5 | 5 | 100.00 |
V1 | TOTAL | 112 | 115 | 97.39 | |||
V2 | long_msg_and_output | kmac_long_msg_and_output | 55.247m | 85.937ms | 49 | 50 | 98.00 |
V2 | burst_write | kmac_burst_write | 27.818m | 15.229ms | 48 | 50 | 96.00 |
V2 | test_vectors | kmac_test_vectors_sha3_224 | 46.812m | 520.419ms | 49 | 50 | 98.00 |
kmac_test_vectors_sha3_256 | 43.645m | 417.129ms | 47 | 50 | 94.00 | ||
kmac_test_vectors_sha3_384 | 33.980m | 154.939ms | 47 | 50 | 94.00 | ||
kmac_test_vectors_sha3_512 | 26.122m | 617.906ms | 49 | 50 | 98.00 | ||
kmac_test_vectors_shake_128 | 1.890h | 1.440s | 48 | 50 | 96.00 | ||
kmac_test_vectors_shake_256 | 1.618h | 1.356s | 45 | 50 | 90.00 | ||
kmac_test_vectors_kmac | 7.570s | 399.770us | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac_xof | 7.430s | 1.347ms | 48 | 50 | 96.00 | ||
V2 | sideload | kmac_sideload | 9.808m | 45.604ms | 49 | 50 | 98.00 |
V2 | app | kmac_app | 7.485m | 14.936ms | 47 | 50 | 94.00 |
V2 | app_with_partial_data | kmac_app_with_partial_data | 7.317m | 60.698ms | 10 | 10 | 100.00 |
V2 | entropy_refresh | kmac_entropy_refresh | 7.156m | 15.091ms | 47 | 50 | 94.00 |
V2 | error | kmac_error | 9.742m | 19.090ms | 48 | 50 | 96.00 |
V2 | key_error | kmac_key_error | 9.970s | 11.190ms | 48 | 50 | 96.00 |
V2 | edn_timeout_error | kmac_edn_timeout_error | 47.810s | 3.851ms | 18 | 20 | 90.00 |
V2 | entropy_mode_error | kmac_entropy_mode_error | 32.860s | 2.420ms | 20 | 20 | 100.00 |
V2 | entropy_ready_error | kmac_entropy_ready_error | 1.525m | 30.967ms | 10 | 10 | 100.00 |
V2 | lc_escalation | kmac_lc_escalation | 44.960s | 2.922ms | 49 | 50 | 98.00 |
V2 | stress_all | kmac_stress_all | 49.959m | 36.830ms | 47 | 50 | 94.00 |
V2 | intr_test | kmac_intr_test | 0.940s | 24.654us | 50 | 50 | 100.00 |
V2 | alert_test | kmac_alert_test | 0.990s | 33.857us | 49 | 50 | 98.00 |
V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.420s | 121.684us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | kmac_tl_errors | 3.420s | 121.684us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.190s | 56.166us | 4 | 5 | 80.00 |
kmac_csr_rw | 1.400s | 427.247us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 11.280s | 1.799ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 3.120s | 256.289us | 19 | 20 | 95.00 | ||
V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.190s | 56.166us | 4 | 5 | 80.00 |
kmac_csr_rw | 1.400s | 427.247us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 11.280s | 1.799ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 3.120s | 256.289us | 19 | 20 | 95.00 | ||
V2 | TOTAL | 1011 | 1050 | 96.29 | |||
V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.560s | 101.490us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.560s | 101.490us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.560s | 101.490us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.560s | 101.490us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.690s | 1.069ms | 19 | 20 | 95.00 |
V2S | tl_intg_err | kmac_sec_cm | 1.973m | 7.865ms | 5 | 5 | 100.00 |
kmac_tl_intg_err | 6.740s | 1.350ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 6.740s | 1.350ms | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 44.960s | 2.922ms | 49 | 50 | 98.00 |
V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.667m | 3.592ms | 48 | 50 | 96.00 |
V2S | sec_cm_key_sideload | kmac_sideload | 9.808m | 45.604ms | 49 | 50 | 98.00 |
V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.560s | 101.490us | 20 | 20 | 100.00 |
V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.973m | 7.865ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.973m | 7.865ms | 5 | 5 | 100.00 |
V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.973m | 7.865ms | 5 | 5 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.667m | 3.592ms | 48 | 50 | 96.00 |
V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 44.960s | 2.922ms | 49 | 50 | 98.00 |
V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.973m | 7.865ms | 5 | 5 | 100.00 |
V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 7.575m | 55.816ms | 10 | 10 | 100.00 |
V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.667m | 3.592ms | 48 | 50 | 96.00 |
V2S | TOTAL | 74 | 75 | 98.67 | |||
V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 42.998m | 261.363ms | 34 | 50 | 68.00 |
V3 | TOTAL | 34 | 50 | 68.00 | |||
TOTAL | 1231 | 1290 | 95.43 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 6 | 75.00 |
V2 | 25 | 25 | 6 | 24.00 |
V2S | 5 | 5 | 4 | 80.00 |
V3 | 2 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.03 | 98.38 | 93.14 | 99.93 | 94.55 | 96.04 | 98.89 | 98.31 |
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 15 failures:
Test kmac_test_vectors_sha3_384 has 1 failures.
4.kmac_test_vectors_sha3_384.86217810232039338823255233066806738124456160779334265379715232671425493367233
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest/run.log
Job ID: smart:bcffb7cf-a388-45ac-95ed-598a04bfa85b
Test kmac_edn_timeout_error has 1 failures.
9.kmac_edn_timeout_error.90112912224093305623230527735973318753818974909186138409825653172679995085409
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest/run.log
Job ID: smart:2fe0ed22-d13b-489e-b184-9c3082d4700d
Test kmac_test_vectors_sha3_256 has 1 failures.
14.kmac_test_vectors_sha3_256.63421460274387622382786686925530246976338669613443767990997300224526885563878
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_sha3_256/latest/run.log
Job ID: smart:16b26af4-abcd-4bcb-8eed-e447da05a247
Test kmac_alert_test has 1 failures.
14.kmac_alert_test.70236632662562010495670173810233873858646292489552692108044057872023935604112
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_alert_test/latest/run.log
Job ID: smart:8ec6ef97-34f0-4388-87db-816480b20a4e
Test kmac_smoke has 1 failures.
21.kmac_smoke.113903241227885096076352025705882305667448488311449852261217615784520353136472
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_smoke/latest/run.log
Job ID: smart:607f00cd-d6cb-47d0-97ef-d8c41b2ddfc5
... and 6 more tests.
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code
has 14 failures:
0.kmac_stress_all_with_rand_reset.86848658373598086157447377894775501904453225227797598020064442236910942506434
Line 1422, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 101743455635 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
UVM_INFO @ 101743455635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.kmac_stress_all_with_rand_reset.73121060497464576333059728584219232788312257873170115736797660655739844960203
Line 415, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 73144577646 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
UVM_INFO @ 73144577646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 7 failures:
Test kmac_test_vectors_shake_256 has 1 failures.
5.kmac_test_vectors_shake_256.12188165740808428360201299700168097086594521794392197091431704751072418000462
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_shake_256/latest/run.log
Job ID: smart:7a3feb0f-ece3-414b-90e7-c65ba634084b
Test kmac_test_vectors_kmac_xof has 2 failures.
10.kmac_test_vectors_kmac_xof.15929774980061775678865953792367609478652656620786025528727102739736471230239
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_kmac_xof/latest/run.log
Job ID: smart:ba9f50e7-4d30-46c3-a8c1-bff16a94ef2a
26.kmac_test_vectors_kmac_xof.27324597698499127194195026682189927059175609333508996044141538815691707159870
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_kmac_xof/latest/run.log
Job ID: smart:65c511c7-3224-49c9-8050-577d97ae83ee
Test kmac_smoke has 1 failures.
11.kmac_smoke.92929620257188760513030899888874291354555040866372216399653734262239641638655
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_smoke/latest/run.log
Job ID: smart:5b481015-950b-4177-8a43-a469472a62ce
Test kmac_app has 1 failures.
22.kmac_app.47813419739880489311614541622002038304350763429405064379962273415623463465429
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_app/latest/run.log
Job ID: smart:a8c89f74-c2f8-4891-8653-348ab1aef86e
Test kmac_lc_escalation has 1 failures.
24.kmac_lc_escalation.111466205726058876544284216666407218794054837794402721359782860175521679945999
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest/run.log
Job ID: smart:0d7c7b40-2448-4dc8-ba3d-c71c69a769bd
... and 1 more tests.
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 4 failures:
Test kmac_burst_write has 1 failures.
11.kmac_burst_write.40018492032424999941654568750898192204485784851115225575242622518300468167871
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_burst_write/latest/run.log
Job ID: smart:6fac7c1a-bb75-4e59-95b9-e10a7f0bec43
Test kmac_key_error has 1 failures.
31.kmac_key_error.74679394033191895636343867853385546249566184188358567615931759690246849844897
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_key_error/latest/run.log
Job ID: smart:e4182745-6359-46d8-be4a-a20ff2cdb903
Test kmac_test_vectors_shake_256 has 1 failures.
41.kmac_test_vectors_shake_256.115522171305703158397128577532363099113126085745588698941178332568066737376537
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_shake_256/latest/run.log
Job ID: smart:0503e37a-491b-4ed5-a3f3-08c724528ecc
Test kmac_test_vectors_sha3_512 has 1 failures.
42.kmac_test_vectors_sha3_512.24944688546155708305143772100634851369239180744051444352818168420547702867579
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_sha3_512/latest/run.log
Job ID: smart:207a2bde-ed94-4dbd-bf39-e3136f61100f
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
has 3 failures:
Test kmac_sideload has 1 failures.
23.kmac_sideload.80703827806814907030929417903255288057318590969161046904402723996954103578817
Line 276, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_sideload/latest/run.log
UVM_ERROR @ 72352531 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 72352531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
26.kmac_stress_all.109433287764464669880888164109986708944739788828626307922769143035729358689844
Line 453, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_stress_all/latest/run.log
UVM_ERROR @ 19484757124 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 19484757124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_384 has 1 failures.
47.kmac_test_vectors_sha3_384.18847187876018822885115418976291843354795830593932241093497078586476710818216
Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_sha3_384/latest/run.log
UVM_ERROR @ 33127535 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 33127535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]
has 2 failures:
Test kmac_entropy_refresh has 1 failures.
9.kmac_entropy_refresh.56348200380524117384294104254199426181152536796778792855706116114792878615376
Line 337, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 2747801742 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (228 [0xe4] vs 12 [0xc]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 2747801742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_app has 1 failures.
24.kmac_app.105027629850255037760562558961274104181111590361870694991013730035284232156598
Line 279, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_app/latest/run.log
UVM_FATAL @ 325671650 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (141 [0x8d] vs 121 [0x79]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 325671650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_masked-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 2 failures:
Test kmac_same_csr_outstanding has 1 failures.
9.kmac_same_csr_outstanding.109917248183761391987464961599451216890551350172466873042824197619849151694021
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest/run.log
Job ID: smart:2ae919e1-4bc2-4145-b53d-d8106180abcd
Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
13.kmac_shadow_reg_errors_with_csr_rw.11206317659423254267390380686839239039701070785927926496385792170518885584085
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
Job ID: smart:ff997694-fb5c-4637-becd-09ab113aa149
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 2 failures:
Test kmac_test_vectors_sha3_384 has 1 failures.
11.kmac_test_vectors_sha3_384.98241920193354487268691780924357070090629949917757763690306480030742914079180
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_sha3_384/latest/run.log
Job ID: smart:44a073c2-0a15-4a00-870f-9a620a209325
Test kmac_test_vectors_sha3_256 has 1 failures.
47.kmac_test_vectors_sha3_256.73987683866434598543792250157031334689976315679739336368856357993068024166138
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_sha3_256/latest/run.log
Job ID: smart:096b55c7-192b-442b-8492-cc186ae4fe54
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 2 failures:
Test kmac_app has 1 failures.
36.kmac_app.113343030517242787159860222774725758603294308503681886585931289712654707454609
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_app/latest/run.log
Job ID: smart:f175d43a-d822-4946-9a4e-0691203bee28
Test kmac_test_vectors_sha3_256 has 1 failures.
41.kmac_test_vectors_sha3_256.77501563989113999190607808026521330125818538223149177691057650798263041216437
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_sha3_256/latest/run.log
Job ID: smart:6abb69ab-8461-4598-8a7f-c5957e6f0497
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request
has 1 failures:
2.kmac_stress_all_with_rand_reset.71601335005051561302788334990653924288462012744420272754491696784639761515352
Line 429, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 25942017003 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 25942017003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_masked-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 1 failures:
4.kmac_csr_hw_reset.98027112548678307155159676677995543247330394992017696601830410562045599443640
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest/run.log
Job ID: smart:48acf4cf-cdaf-4a8a-81f5-54b550c2840c
UVM_ERROR (kmac_edn_timeout_error_vseq.sv:68) [kmac_edn_timeout_error_vseq] Check failed cfg.m_kmac_app_agent_cfg[AppKeymgr].vif.kmac_data_rsp.error == * (* [*] vs * [*])
has 1 failures:
6.kmac_edn_timeout_error.57629309431483618381792627363627627178954950740604082181345840550619065384291
Line 283, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest/run.log
UVM_ERROR @ 1275634853 ps: (kmac_edn_timeout_error_vseq.sv:68) [uvm_test_top.env.virtual_sequencer.kmac_edn_timeout_error_vseq] Check failed cfg.m_kmac_app_agent_cfg[AppKeymgr].vif.kmac_data_rsp.error == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1275634853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: Job lost from admin server: generic::not_found: generic::not_found: job is not found
has 1 failures:
18.kmac_test_vectors_shake_128.25841673033995386809674252904303706446597538568402851165121879533676652512770
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_shake_128/latest/run.log
Job ID: smart:ef7f19ba-a202-48e4-b535-f91788f3905c
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 1 failures:
19.kmac_error.16465215241575118209882502474210360374678387452256304818601086264111927902316
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_error/latest/run.log
Job ID: smart:5f19c3fc-806e-48be-8c07-5c412b8e5761
Exit reason: Error: User command failed Job returned non-zero exit code
has 1 failures:
20.kmac_test_vectors_shake_128.59660504809883356972937136409895595681618484781083130234576970085019197695212
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_shake_128/latest/run.log
[make]: simulate
cd /workspace/20.kmac_test_vectors_shake_128/latest && /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295995116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.3295995116 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 24 17:02 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
21.kmac_burst_write.54512354670326246424106105026422305271048508891848369004543079260654582709964
Line 346, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*]
has 1 failures:
41.kmac_stress_all_with_rand_reset.3119934395338340828765693528081279566962392435788178324869652329453340591297
Line 291, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 342229967 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (71 [0x47] vs 201 [0xc9]) Mismatch between exp_digest[0] and act_digest[0]
UVM_INFO @ 342229967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---