KMAC/MASKED Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.496m	11.295ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	162.182us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.280s	35.298us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.850s	3.763ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.640s	582.549us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.290s	115.561us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.280s	35.298us	20	20	100.00
		kmac_csr_aliasing	11.640s	582.549us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	22.031us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.610s	135.061us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.738m	95.025ms	49	50	98.00
V2	burst_write	kmac_burst_write	28.318m	46.139ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.914m	896.766ms	50	50	100.00
		kmac_test_vectors_sha3_256	52.978m	1.868s	50	50	100.00
		kmac_test_vectors_sha3_384	33.346m	147.776ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.796m	214.819ms	50	50	100.00
		kmac_test_vectors_shake_128	1.946h	1.874s	49	50	98.00
		kmac_test_vectors_shake_256	1.720h	2.410s	50	50	100.00
		kmac_test_vectors_kmac	7.290s	954.847us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.670s	2.202ms	50	50	100.00
V2	sideload	kmac_sideload	10.375m	23.346ms	50	50	100.00
V2	app	kmac_app	7.650m	51.224ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.117m	82.800ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.295m	196.194ms	50	50	100.00
V2	error	kmac_error	8.749m	15.625ms	50	50	100.00
V2	key_error	kmac_key_error	6.730s	2.212ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.830s	7.776ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.640s	1.094ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.474m	32.379ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	46.220s	5.935ms	50	50	100.00
V2	stress_all	kmac_stress_all	59.952m	653.614ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.870s	64.337us	50	50	100.00
V2	alert_test	kmac_alert_test	0.950s	33.773us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.680s	146.640us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.680s	146.640us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	162.182us	5	5	100.00
		kmac_csr_rw	1.280s	35.298us	20	20	100.00
		kmac_csr_aliasing	11.640s	582.549us	5	5	100.00
		kmac_same_csr_outstanding	2.960s	973.418us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	162.182us	5	5	100.00
		kmac_csr_rw	1.280s	35.298us	20	20	100.00
		kmac_csr_aliasing	11.640s	582.549us	5	5	100.00
		kmac_same_csr_outstanding	2.960s	973.418us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.730s	278.887us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.730s	278.887us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.730s	278.887us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.730s	278.887us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.390s	567.557us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.992m	10.831ms	5	5	100.00
		kmac_tl_intg_err	6.770s	5.002ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.770s	5.002ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	46.220s	5.935ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.496m	11.295ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.375m	23.346ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.730s	278.887us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.992m	10.831ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.992m	10.831ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.992m	10.831ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.496m	11.295ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	46.220s	5.935ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.992m	10.831ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.297m	20.655ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.496m	11.295ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.525h	268.340ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1264	1290	97.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	98.38	93.14	99.93	95.45	96.04	98.89	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 15 failures:
- Test kmac_stress_all_with_rand_reset has 15 failures.
  - 0.kmac_stress_all_with_rand_reset.17873068205498522052359471867815940633985706491192991218841223814635559632409
    Line 820, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 79080616674 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 79080616674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.2824410256372005481932578569047285719112831593720950704870886534642562658123
    Line 1239, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 119283655967 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 119283655967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all has 2 failures.
  - 0.kmac_stress_all.28480888699480760400003088896984786368034134276026695213897988014007515833259
    Line 1022, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 52798387848 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 52798387848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.kmac_stress_all.28232074147422306314879552016028870587346891342761382025637898214930267601998
    Line 463, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 34513549233 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 34513549233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 30.kmac_stress_all_with_rand_reset.52249673721543642332144597979026559774944859693202869114689385858242453942919
    Line 1010, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 138231433044 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 138231433044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.kmac_stress_all_with_rand_reset.61900596434838080813683075777192742115724687985818649482241893342491862951637
    Line 609, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 13798966523 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 13798966523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_mubi has 1 failures.

0.kmac_mubi.81200190737071603576247015619925851588651734410259863581680530979931637856530
Line 1180, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_mubi/latest/run.log

  UVM_FATAL @ 20654586672 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (164 [0xa4] vs 84 [0x54]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 20654586672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app_with_partial_data has 1 failures.

9.kmac_app_with_partial_data.48575345473205815591128908306513982161423126797198632801534739924529450781476
Line 690, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 31230918526 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (113 [0x71] vs 15 [0xf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 31230918526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

10.kmac_stress_all_with_rand_reset.58128577797082865137026780143439621505971111881383947861630675243910532744573
Line 1743, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 97649932961 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (73 [0x49] vs 89 [0x59]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 97649932961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 28.kmac_test_vectors_shake_128.41790860035580747503176637564876643344850795794629598772785524164199609986065
    Line 5388, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 31.kmac_burst_write.43119457569588609761788007522023428469589581925821352771296673386945350957462
    Line 867, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_app has 1 failures.
  - 41.kmac_app.105408162000515817381639658195358699758463075576999211127463946220313280844584
    Line 1085, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 49.kmac_long_msg_and_output.98410463087916931058027126976035012713159678668261174475848893299332698823121
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:5a7e782a-5baf-4986-a378-3ccba7c4665b
```