KMAC/MASKED Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.612m	17.943ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.240s	130.793us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.340s	271.210us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.910s	17.225ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.560s	1.893ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.730s	36.389us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.340s	271.210us	20	20	100.00
		kmac_csr_aliasing	11.560s	1.893ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	16.307us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	46.766us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	58.851m	521.510ms	49	50	98.00
V2	burst_write	kmac_burst_write	27.254m	112.594ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.716m	99.679ms	50	50	100.00
		kmac_test_vectors_sha3_256	47.878m	1.598s	50	50	100.00
		kmac_test_vectors_sha3_384	31.473m	151.220ms	50	50	100.00
		kmac_test_vectors_sha3_512	29.591m	965.841ms	50	50	100.00
		kmac_test_vectors_shake_128	1.976h	2.350s	50	50	100.00
		kmac_test_vectors_shake_256	1.579h	914.892ms	50	50	100.00
		kmac_test_vectors_kmac	7.470s	323.770us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.260s	302.171us	50	50	100.00
V2	sideload	kmac_sideload	8.803m	95.980ms	50	50	100.00
V2	app	kmac_app	7.685m	37.488ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.887m	8.964ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.927m	25.344ms	49	50	98.00
V2	error	kmac_error	8.745m	10.596ms	49	50	98.00
V2	key_error	kmac_key_error	7.900s	1.269ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	58.890s	3.748ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	30.440s	3.756ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.493m	8.345ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	45.960s	2.956ms	50	50	100.00
V2	stress_all	kmac_stress_all	45.916m	248.571ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.990s	14.328us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	65.331us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.500s	139.755us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.500s	139.755us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.240s	130.793us	5	5	100.00
		kmac_csr_rw	1.340s	271.210us	20	20	100.00
		kmac_csr_aliasing	11.560s	1.893ms	5	5	100.00
		kmac_same_csr_outstanding	3.080s	540.471us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.240s	130.793us	5	5	100.00
		kmac_csr_rw	1.340s	271.210us	20	20	100.00
		kmac_csr_aliasing	11.560s	1.893ms	5	5	100.00
		kmac_same_csr_outstanding	3.080s	540.471us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.600s	63.463us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.600s	63.463us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.600s	63.463us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.600s	63.463us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.250s	132.172us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.927m	9.441ms	5	5	100.00
		kmac_tl_intg_err	6.180s	2.633ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.180s	2.633ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	45.960s	2.956ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.612m	17.943ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.803m	95.980ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.600s	63.463us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.927m	9.441ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.927m	9.441ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.927m	9.441ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.612m	17.943ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	45.960s	2.956ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.927m	9.441ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.045m	17.830ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.612m	17.943ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.289h	287.187ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			1270	1290	98.45

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	98.38	93.15	99.93	95.45	96.04	98.89	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.51340887053635461939297795927305665507036234990830709635567394175713556817627
    Line 1204, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 78169646575 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 78169646575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.60355786694836466251169902421325193699519495363872106465932380016797941954134
    Line 284, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 139259573 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 139259573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 6 failures:
- Test kmac_stress_all has 1 failures.
  - 17.kmac_stress_all.115674060930295578980360036475970399417964210819616588496880364388538041581848
    Line 388, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 150533214785 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 150533214785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 23.kmac_stress_all_with_rand_reset.23038201484716524570773709868412657447082062133349370394564132919288731154689
    Line 1227, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 64283822882 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 64283822882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.kmac_stress_all_with_rand_reset.74236551686384471395566485962628596037621746422322442374062161792001700947983
    Line 773, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 22066121343 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 22066121343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test kmac_error has 1 failures.
  - 46.kmac_error.93135209022074879027716874160254517723088687487415378254471045253709614644029
    Line 291, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_error/latest/run.log
```
  UVM_FATAL @ 10371545093 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10371545093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 1 failures.

27.kmac_entropy_refresh.10813846032357215894235192685969132695334265153937211496119834286178866834971
Line 286, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 364488696 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (213 [0xd5] vs 102 [0x66]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 364488696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

28.kmac_app.87356705843446712355786542619192397359091970268409827438038312928657856109045
Line 334, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_app/latest/run.log

  UVM_FATAL @ 7516059290 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (225 [0xe1] vs 235 [0xeb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7516059290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

28.kmac_stress_all.87841085315265109701653966152745794388423435059635823519126161096265584337615
Line 349, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_stress_all/latest/run.log

  UVM_FATAL @ 37911070325 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (67 [0x43] vs 241 [0xf1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 37911070325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 32.kmac_key_error.115712773942414173618177055177715527438542324519700850606424690407426237910148
    Line 278, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 164996016 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 164996016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_smoke has 1 failures.
  - 42.kmac_smoke.19566246984630777361292241820180658079160757145781306459423324789560665724616
    Line 276, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_smoke/latest/run.log
```
  UVM_ERROR @  34520071 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  34520071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 42.kmac_long_msg_and_output.89583520287499660753117201501946290620762454604616950460100902135760334129442
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:f19ee93f-3c0d-49c2-93a1-da008a8064b9
```