KMAC/MASKED Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.697m	18.213ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.230s	40.402us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	26.648us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	24.960s	12.861ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.480s	1.831ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.410s	133.772us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	26.648us	20	20	100.00
		kmac_csr_aliasing	11.480s	1.831ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	13.128us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	273.106us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.435m	122.496ms	47	50	94.00
V2	burst_write	kmac_burst_write	29.425m	14.581ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	49.091m	468.440ms	50	50	100.00
		kmac_test_vectors_sha3_256	45.511m	365.972ms	50	50	100.00
		kmac_test_vectors_sha3_384	42.178m	1.394s	50	50	100.00
		kmac_test_vectors_sha3_512	26.282m	106.345ms	50	50	100.00
		kmac_test_vectors_shake_128	1.960h	926.331ms	48	50	96.00
		kmac_test_vectors_shake_256	1.750h	2.376s	50	50	100.00
		kmac_test_vectors_kmac	8.510s	1.582ms	49	50	98.00
		kmac_test_vectors_kmac_xof	8.730s	924.841us	50	50	100.00
V2	sideload	kmac_sideload	9.779m	50.221ms	50	50	100.00
V2	app	kmac_app	8.088m	6.248ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.085m	24.372ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.208m	125.018ms	49	50	98.00
V2	error	kmac_error	10.204m	62.059ms	50	50	100.00
V2	key_error	kmac_key_error	11.600s	18.716ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.097m	639.788us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.160s	1.945ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.334m	15.423ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	29.120s	790.440us	50	50	100.00
V2	stress_all	kmac_stress_all	43.399m	245.312ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.900s	53.650us	50	50	100.00
V2	alert_test	kmac_alert_test	0.980s	21.969us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.380s	502.681us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.380s	502.681us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.230s	40.402us	5	5	100.00
		kmac_csr_rw	1.260s	26.648us	20	20	100.00
		kmac_csr_aliasing	11.480s	1.831ms	5	5	100.00
		kmac_same_csr_outstanding	2.990s	730.994us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.230s	40.402us	5	5	100.00
		kmac_csr_rw	1.260s	26.648us	20	20	100.00
		kmac_csr_aliasing	11.480s	1.831ms	5	5	100.00
		kmac_same_csr_outstanding	2.990s	730.994us	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.670s	55.401us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.670s	55.401us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.670s	55.401us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.670s	55.401us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.400s	583.957us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.124m	58.590ms	5	5	100.00
		kmac_tl_intg_err	6.100s	305.482us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.100s	305.482us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	29.120s	790.440us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.697m	18.213ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.779m	50.221ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.670s	55.401us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.124m	58.590ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.124m	58.590ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.124m	58.590ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.697m	18.213ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	29.120s	790.440us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.124m	58.590ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.618m	5.783ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.697m	18.213ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	44.831m	79.024ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			1270	1290	98.45

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	98.38	93.14	99.93	95.45	96.04	98.89	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 7.kmac_stress_all_with_rand_reset.83694751909215893200677479265156122905436190136928182474251441196375390048829
    Line 293, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1803840779 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1803840779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.kmac_stress_all_with_rand_reset.236192686183794788251999775504607855329591036296237940258931405944032194498
    Line 677, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 207913831956 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 207913831956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test kmac_long_msg_and_output has 3 failures.
  - 15.kmac_long_msg_and_output.67139389103629426975654105180010156537580776156149216819314094832263787484028
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:0905e277-2a68-4440-a1ac-ae2cb732f6e9
```
  - 19.kmac_long_msg_and_output.1614324562511456519508818363377279767469373613364363333191278850956795346881
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:3bdc050e-c805-4f43-b4a3-12711a5b80b6
```
  - ... and 1 more failures.
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 16.kmac_test_vectors_shake_128.21492057276289720778040206785373201818914837466034190833054484033392616814838
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:adae50d2-8f7e-4615-8bd7-8d022fa79af7
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_burst_write has 2 failures.
  - 21.kmac_burst_write.92912279495065758854444440031270442950164245250104818448876825837449333372505
    Line 367, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.kmac_burst_write.27879681671725062301123758708521387111019143135396118413915896432875346007004
    Line 351, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 49.kmac_entropy_refresh.74311057237829007944773164653136883618008407521993262204680696080601172831412
    Line 423, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 22.kmac_stress_all_with_rand_reset.96557491601537599835955620406531006303395447626171600350822146155985761779580
    Line 567, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 31142755606 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 31142755606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.kmac_stress_all_with_rand_reset.95865438809808862844606569966144910319991171679560213012261896984560098927465
    Line 1525, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 659022415519 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 659022415519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 1.kmac_test_vectors_shake_128.6987650579788010322324475206941800873874617229842334533916380295142806854518
    Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @ 325318312 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 325318312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac has 1 failures.
  - 22.kmac_test_vectors_kmac.96506681763751112706630618628608593543249612709706156721876461865834906837436
    Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  81202846 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  81202846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 9.kmac_stress_all_with_rand_reset.80983437118988480754655361114772398078883619927367363073357146019723153158496
    Line 589, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 25813333872 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (124 [0x7c] vs 28 [0x1c]) Mismatch between exp_digest[44] and act_digest[44]
  UVM_INFO @ 25813333872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 11.kmac_stress_all_with_rand_reset.14563377480807946186989636448726411169136198847410671836315916053160261872408
    Line 295, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 746759384 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (255 [0xff] vs 226 [0xe2]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 746759384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/MASKED Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: 796f9fb805

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `796f9fb805`