KMAC/MASKED Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.755m	8.945ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	100.010us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.390s	28.595us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	25.290s	7.733ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.570s	1.613ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.280s	766.397us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.390s	28.595us	20	20	100.00
		kmac_csr_aliasing	11.570s	1.613ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	103.161us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	22.400us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.700m	269.201ms	47	50	94.00
V2	burst_write	kmac_burst_write	28.784m	62.742ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.096m	1.110s	49	50	98.00
		kmac_test_vectors_sha3_256	48.721m	1.663s	50	50	100.00
		kmac_test_vectors_sha3_384	33.214m	302.074ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.489m	550.969ms	50	50	100.00
		kmac_test_vectors_shake_128	1.905h	3.202s	50	50	100.00
		kmac_test_vectors_shake_256	1.620h	1.380s	50	50	100.00
		kmac_test_vectors_kmac	10.320s	1.294ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.650s	408.747us	50	50	100.00
V2	sideload	kmac_sideload	8.925m	15.435ms	50	50	100.00
V2	app	kmac_app	7.720m	23.961ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.534m	194.488ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.954m	110.780ms	48	50	96.00
V2	error	kmac_error	9.268m	88.232ms	49	50	98.00
V2	key_error	kmac_key_error	9.830s	11.499ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	37.230s	2.194ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	53.450s	4.469ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	52.880s	5.107ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	26.710s	3.342ms	50	50	100.00
V2	stress_all	kmac_stress_all	39.277m	25.667ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.990s	15.062us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	23.611us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.830s	242.527us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.830s	242.527us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	100.010us	5	5	100.00
		kmac_csr_rw	1.390s	28.595us	20	20	100.00
		kmac_csr_aliasing	11.570s	1.613ms	5	5	100.00
		kmac_same_csr_outstanding	3.110s	128.918us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	100.010us	5	5	100.00
		kmac_csr_rw	1.390s	28.595us	20	20	100.00
		kmac_csr_aliasing	11.570s	1.613ms	5	5	100.00
		kmac_same_csr_outstanding	3.110s	128.918us	20	20	100.00
V2		TOTAL			1036	1050	98.67
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.550s	192.494us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.550s	192.494us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.550s	192.494us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.550s	192.494us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.570s	2.113ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.220m	42.201ms	5	5	100.00
		kmac_tl_intg_err	5.760s	919.517us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.760s	919.517us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	26.710s	3.342ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.755m	8.945ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.925m	15.435ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.550s	192.494us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.220m	42.201ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.220m	42.201ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.220m	42.201ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.755m	8.945ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	26.710s	3.342ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.220m	42.201ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.339m	26.400ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.755m	8.945ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	51.761m	121.024ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			1242	1290	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.01	98.38	93.14	99.93	94.55	96.04	98.89	98.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 25 failures:
- Test kmac_stress_all_with_rand_reset has 25 failures.
  - 1.kmac_stress_all_with_rand_reset.102414628319395226719652020942063759756764230561752690374922829065973598692906
    Line 688, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9551839912 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 9551839912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.106527607043571815875737524337824345643084601197010432922550037288433080313873
    Line 306, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 275790842 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 275790842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 14.kmac_stress_all_with_rand_reset.30024044292486548549796416692944747929062234785611890823204923842157745380928
    Line 1178, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41843364484 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 41843364484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.kmac_stress_all_with_rand_reset.92692050429300261472522347470326436319580880275670335941873032326767366013244
    Line 509, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15072563929 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 15072563929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_entropy_refresh has 2 failures.

4.kmac_entropy_refresh.45560131078279495930007928976209964443989190628055731908332021613488698682671
Line 540, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 8835566468 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (224 [0xe0] vs 165 [0xa5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8835566468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.kmac_entropy_refresh.108028808596476941259455991084570288430149924523417097943573089039932687857736
Line 414, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 9246707470 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (81 [0x51] vs 115 [0x73]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9246707470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

5.kmac_stress_all.81333687217046111363020932221149104068766189701278247272612454405181624999910
Line 1432, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all/latest/run.log

  UVM_FATAL @ 17682263012 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (216 [0xd8] vs 213 [0xd5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17682263012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.kmac_stress_all.111410488467753388139741568668742910247308852627654899410655166825285760749663
Line 948, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all/latest/run.log

  UVM_FATAL @ 109185899819 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (116 [0x74] vs 41 [0x29]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 109185899819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

8.kmac_app.4668206381560181042463243857334485799717642068598587882068448163661741669993
Line 608, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_app/latest/run.log

  UVM_FATAL @ 6725563530 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (63 [0x3f] vs 137 [0x89]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6725563530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 5 failures:
- Test kmac_error has 1 failures.
  - 11.kmac_error.70897376420631318397251984485715787139560461665741144220615525423299374139767
    Line 566, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_error/latest/run.log
```
  UVM_FATAL @ 10161212313 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10161212313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 2 failures.
  - 14.kmac_stress_all.3562578366188049862042510909405073469636779342772979895473034597257505000784
    Line 633, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 22935569749 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 22935569749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.kmac_stress_all.10702977522521880282700250470505871687431194212407113250703935608118123130447
    Line 1223, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 206026802975 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 206026802975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 23.kmac_stress_all_with_rand_reset.87102418148637651525129397798254364805313894304883653555010535936999751752013
    Line 934, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 26016706703 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 26016706703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.kmac_stress_all_with_rand_reset.64894881191976278420692944892679615206446058113026851923543885927684740866540
    Line 763, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 27655444004 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 27655444004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test kmac_long_msg_and_output has 3 failures.
  - 18.kmac_long_msg_and_output.59499603570961441411693992077159748512532174037221646597461928908580239224709
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:26658ef8-f635-4c24-ae20-61e78bfe8ba7
```
  - 28.kmac_long_msg_and_output.44955984403059244026647291322166412607183948886159227070256039704015008196606
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:8407cdbf-b577-4dce-94cf-b36d6f45a994
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 1 failures.
  - 8.kmac_burst_write.41884984783583048926969341243186560548321393303943462635600164199146950643600
    Line 585, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_app has 1 failures.
  - 44.kmac_app.98088849024757143795005868716503324249642996255583909668466401701311216810768
    Line 795, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 33.kmac_test_vectors_sha3_224.678766789675532359972326109783989473219515116202615011900868916053050489394
    Line 278, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  25803325 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  25803325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```