49a27e136c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.657m | 17.672ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.180s | 63.520us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.370s | 464.390us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 21.770s | 2.011ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 11.490s | 531.842us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 3.190s | 207.874us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.370s | 464.390us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 11.490s | 531.842us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.780s | 36.169us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.460s | 44.586us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 59.265m | 128.894ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 27.163m | 56.436ms | 48 | 50 | 96.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 46.383m | 691.489ms | 50 | 50 | 100.00 |
| kmac_test_vectors_sha3_256 | 49.621m | 1.523s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 36.955m | 1.229s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 26.925m | 723.818ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.888h | 1.302s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_256 | 1.726h | 1.842s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac | 8.140s | 4.934ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 7.480s | 1.381ms | 50 | 50 | 100.00 | ||
| V2 | sideload | kmac_sideload | 9.710m | 101.711ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 8.108m | 39.703ms | 49 | 50 | 98.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 7.031m | 14.843ms | 9 | 10 | 90.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 7.081m | 16.718ms | 49 | 50 | 98.00 |
| V2 | error | kmac_error | 9.890m | 89.682ms | 49 | 50 | 98.00 |
| V2 | key_error | kmac_key_error | 8.890s | 10.553ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 52.660s | 1.982ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 26.920s | 1.278ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.221m | 28.603ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 49.130s | 1.142ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 58.343m | 134.959ms | 48 | 50 | 96.00 |
| V2 | intr_test | kmac_intr_test | 0.860s | 15.591us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.990s | 29.776us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.740s | 211.471us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.740s | 211.471us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.180s | 63.520us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.370s | 464.390us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 11.490s | 531.842us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.260s | 2.319ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.180s | 63.520us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.370s | 464.390us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 11.490s | 531.842us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.260s | 2.319ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1042 | 1050 | 99.24 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.650s | 79.177us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.650s | 79.177us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.650s | 79.177us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.650s | 79.177us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.340s | 737.442us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.766m | 30.462ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.890s | 1.079ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.890s | 1.079ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 49.130s | 1.142ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.657m | 17.672ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 9.710m | 101.711ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.650s | 79.177us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.766m | 30.462ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.766m | 30.462ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.766m | 30.462ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.657m | 17.672ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 49.130s | 1.142ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.766m | 30.462ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 7.881m | 14.174ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.657m | 17.672ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 46.256m | 151.130ms | 13 | 50 | 26.00 |
| V3 | TOTAL | 13 | 50 | 26.00 | |||
| TOTAL | 1245 | 1290 | 96.51 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 19 | 76.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.96 | 98.38 | 93.14 | 99.69 | 94.55 | 96.04 | 98.89 | 98.03 |
UVM_ERROR (cip_base_vseq.sv:774) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 26 failures:
2.kmac_stress_all_with_rand_reset.31470001554340385298835344929129850294206168840187068238921709608068068634165
Line 287, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2131946429 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 2131946429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.kmac_stress_all_with_rand_reset.91460348769458658468213520200982403797860574645420435885473407676914491057130
Line 429, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 155448538174 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 155448538174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
0.kmac_stress_all_with_rand_reset.65699468727601020983002915725621843556842411235505870447580765932151170340562
Line 288, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 247374513 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
UVM_INFO @ 247374513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.kmac_stress_all_with_rand_reset.24685728106376187988421001219559972506129446139701372575755632123129940134993
Line 695, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10907685796 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
UVM_INFO @ 10907685796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
Test kmac_error has 1 failures.
0.kmac_error.63432031933322575912828980638693886370671246539379106390211612268826232654346
Line 986, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_app_with_partial_data has 1 failures.
5.kmac_app_with_partial_data.62886021651372408021924133281060565878783528871748407968108506812155917418843
Line 1023, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_app has 1 failures.
19.kmac_app.92140869457599926224700653052957891222918781700965211285407956956050201407887
Line 941, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_app/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_burst_write has 2 failures.
24.kmac_burst_write.93292094801951994715477622033101721655208278396250299278346520662570787844299
Line 1041, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.kmac_burst_write.110467833672217133918144679560752941892057732058193958927768321533388358370290
Line 717, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
1.kmac_stress_all_with_rand_reset.52165293366862994312364788677889185932690674471285916020343089342507237164932
Line 742, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11268127489 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 11268127489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.kmac_stress_all_with_rand_reset.81395425735228721708292825317112816648236600249105517093940718850694213293576
Line 568, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10707766655 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10707766655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
43.kmac_stress_all.114583257757467010846950375427488577442341722740379909452412933408375797494507
Line 1735, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_stress_all/latest/run.log
UVM_FATAL @ 129945651058 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 129945651058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
Test kmac_entropy_refresh has 1 failures.
28.kmac_entropy_refresh.83283105082207583380890212972594264545087473208309342247406851573928110451704
Line 380, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 1679868504 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (73 [0x49] vs 115 [0x73]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 1679868504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
44.kmac_stress_all.85549274787208534773484588899714424827406839003530173585010691156081751424384
Line 1172, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_stress_all/latest/run.log
UVM_FATAL @ 16848684513 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (222 [0xde] vs 129 [0x81]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 16848684513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---