KMAC/MASKED Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: `32ed2c4230`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.757m	16.915ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.080s	56.275us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.270s	77.969us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.170s	1.545ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.910s	455.532us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.810s	34.834us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.270s	77.969us	20	20	100.00
		kmac_csr_aliasing	10.910s	455.532us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	19.507us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	40.561us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	53.499m	1.256s	49	50	98.00
V2	burst_write	kmac_burst_write	30.280m	58.656ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	45.602m	99.241ms	50	50	100.00
		kmac_test_vectors_sha3_256	42.520m	1.135s	50	50	100.00
		kmac_test_vectors_sha3_384	37.085m	684.647ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.033m	109.626ms	50	50	100.00
		kmac_test_vectors_shake_128	1.958h	1.125s	49	50	98.00
		kmac_test_vectors_shake_256	1.655h	922.908ms	50	50	100.00
		kmac_test_vectors_kmac	8.230s	639.859us	50	50	100.00
		kmac_test_vectors_kmac_xof	8.180s	271.365us	50	50	100.00
V2	sideload	kmac_sideload	10.153m	94.352ms	50	50	100.00
V2	app	kmac_app	7.142m	32.913ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.729m	40.999ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.730m	15.684ms	47	50	94.00
V2	error	kmac_error	9.135m	123.850ms	49	50	98.00
V2	key_error	kmac_key_error	12.290s	23.064ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	53.800s	6.311ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.910s	3.116ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.327m	8.510ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	50.030s	10.029ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.032h	37.525ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.890s	16.358us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	119.533us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.360s	110.346us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.360s	110.346us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.080s	56.275us	5	5	100.00
		kmac_csr_rw	1.270s	77.969us	20	20	100.00
		kmac_csr_aliasing	10.910s	455.532us	5	5	100.00
		kmac_same_csr_outstanding	3.080s	474.415us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.080s	56.275us	5	5	100.00
		kmac_csr_rw	1.270s	77.969us	20	20	100.00
		kmac_csr_aliasing	10.910s	455.532us	5	5	100.00
		kmac_same_csr_outstanding	3.080s	474.415us	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.580s	195.305us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.580s	195.305us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.580s	195.305us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.580s	195.305us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.180s	363.476us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.082m	17.054ms	5	5	100.00
		kmac_tl_intg_err	6.150s	583.593us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.150s	583.593us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	50.030s	10.029ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.757m	16.915ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.153m	94.352ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.580s	195.305us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.082m	17.054ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.082m	17.054ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.082m	17.054ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.757m	16.915ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	50.030s	10.029ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.082m	17.054ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.665m	21.196ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.757m	16.915ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	59.030m	448.878ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			1246	1290	96.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.01	98.38	93.14	99.93	94.55	96.04	98.89	98.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:788) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test kmac_stress_all_with_rand_reset has 30 failures.
  - 1.kmac_stress_all_with_rand_reset.60249678149262587052970666398675205747709722189138035865729308237477392134123
    Line 972, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22214783868 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 22214783868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.21938690679523509252457048950914064283991786483613471579034244415536048857005
    Line 588, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27544818029 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 27544818029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 20.kmac_stress_all_with_rand_reset.46685951234354527648871158974071183288491405245305164538197023142706795257833
    Line 1399, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 194275023424 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 194275023424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.kmac_stress_all_with_rand_reset.72041807492664169945395922477359847936698617430380791713146007481501008560581
    Line 287, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  34231664 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @  34231664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 14.kmac_test_vectors_shake_128.46665608380128247989613779150243832289633633775169135710582423486473228203432
    Line 4875, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 2 failures.
  - 26.kmac_burst_write.70252325350754922199134939225098815129160429977836183875009431885058836741911
    Line 771, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.kmac_burst_write.35259965535520387802968238615299722571463468565184108261242041692296006603473
    Line 1101, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_entropy_refresh has 2 failures.

9.kmac_entropy_refresh.72039935142197689187899320036976471613933457036259009004626402465491792667796
Line 430, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3941975453 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (97 [0x61] vs 176 [0xb0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3941975453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.kmac_entropy_refresh.107645309519305350138191010549852215730989057457156900164721515931681229195802
Line 326, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3653101633 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (235 [0xeb] vs 241 [0xf1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3653101633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_error has 1 failures.
  - 12.kmac_error.65267074638435646935666206044260819807678780830581713080575390382949302005746
    Line 570, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_error/latest/run.log
```
  UVM_FATAL @ 10048616369 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10048616369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 12.kmac_stress_all_with_rand_reset.103588336846241030985025379046264239839886005096669525318984851502465762121677
    Line 589, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10904375649 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10904375649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 2.kmac_long_msg_and_output.70498925789249401089512282458296792539369760180942946134406090483586954600711
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:b4098bc3-befb-4bbc-8f2c-49e990aa42db
```
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 8.kmac_entropy_refresh.57272782842633386134531649801722399697196086825590513526670343119142615207559
    Line 397, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest/run.log
```
  UVM_ERROR @ 2521373809 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 2521373809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```