KMAC/MASKED Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.489m	4.002ms	47	50	94.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	56.022us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	120.561us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.460s	10.274ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.990s	4.261ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.570s	143.283us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	120.561us	20	20	100.00
		kmac_csr_aliasing	8.990s	4.261ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	88.351us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.470s	45.248us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	long_msg_and_output	kmac_long_msg_and_output	59.829m	500.242ms	50	50	100.00
V2	burst_write	kmac_burst_write	28.036m	29.746ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	45.659m	979.979ms	50	50	100.00
		kmac_test_vectors_sha3_256	48.590m	1.300s	50	50	100.00
		kmac_test_vectors_sha3_384	32.455m	743.837ms	46	50	92.00
		kmac_test_vectors_sha3_512	23.604m	45.082ms	47	50	94.00
		kmac_test_vectors_shake_128	1.894h	3.574s	49	50	98.00
		kmac_test_vectors_shake_256	1.627h	2.966s	47	50	94.00
		kmac_test_vectors_kmac	8.370s	4.320ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.430s	1.304ms	50	50	100.00
V2	sideload	kmac_sideload	8.723m	10.740ms	49	50	98.00
V2	app	kmac_app	6.260m	61.252ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.556m	13.787ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.150m	18.533ms	48	50	96.00
V2	error	kmac_error	9.011m	56.655ms	49	50	98.00
V2	key_error	kmac_key_error	7.400s	1.087ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	56.290s	16.353ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.020s	573.194us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.023m	22.326ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	31.630s	2.985ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.035h	95.479ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.870s	13.968us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	31.005us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.080s	979.783us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.080s	979.783us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	56.022us	5	5	100.00
		kmac_csr_rw	1.260s	120.561us	20	20	100.00
		kmac_csr_aliasing	8.990s	4.261ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	1.406ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	56.022us	5	5	100.00
		kmac_csr_rw	1.260s	120.561us	20	20	100.00
		kmac_csr_aliasing	8.990s	4.261ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	1.406ms	20	20	100.00
V2		TOTAL			1030	1050	98.10
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.680s	213.124us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.680s	213.124us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.680s	213.124us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.680s	213.124us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.120s	258.611us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.902m	9.130ms	5	5	100.00
		kmac_tl_intg_err	5.200s	1.111ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.200s	1.111ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	31.630s	2.985ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.489m	4.002ms	47	50	94.00
V2S	sec_cm_key_sideload	kmac_sideload	8.723m	10.740ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.680s	213.124us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.902m	9.130ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.902m	9.130ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.902m	9.130ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.489m	4.002ms	47	50	94.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	31.630s	2.985ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.902m	9.130ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.082m	95.371ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.489m	4.002ms	47	50	94.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	28.755m	37.470ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			1228	1290	95.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	16	64.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	98.15	92.62	99.89	96.36	96.04	98.89	98.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:788) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test kmac_stress_all_with_rand_reset has 30 failures.
  - 1.kmac_stress_all_with_rand_reset.48604651658698685083710548033453924731938167191127736363995522622649172236629
    Line 1414, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17541356905 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17541356905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.73897890127391868000902852742898354167085861337973407882453844549476253905562
    Line 849, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14657491585 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14657491585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.

UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 16 failures:

Test kmac_smoke has 3 failures.

1.kmac_smoke.53562409628823787233641587240932265589928701371852719416259165352982650350860
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_smoke/latest/run.log

  UVM_ERROR @  44743213 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  44743213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_smoke.43258667402071635386024559272505257653310237327614100274885243699241659828319
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_smoke/latest/run.log

  UVM_ERROR @  38237640 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  38237640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_test_vectors_shake_128 has 1 failures.

1.kmac_test_vectors_shake_128.31700504653713992974141308935182678983328084621384971574663543873750649249212
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log

  UVM_ERROR @  76471696 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  76471696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_error has 1 failures.

5.kmac_error.30765566837576370642035532804377876332660939326439570378119503607678713752531
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_error/latest/run.log

  UVM_ERROR @  38901768 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  38901768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_512 has 3 failures.

6.kmac_test_vectors_sha3_512.13687971563353069879593785989105100587032984918040487722032656962387472411130
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  52716859 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  52716859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.kmac_test_vectors_sha3_512.32073840870958937693533798743171441630053530169834608328755497802010783097812
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  49333088 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  49333088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_test_vectors_shake_256 has 3 failures.

6.kmac_test_vectors_shake_256.15127259214766029539251829383548331450597997781873317973608198563280331901223
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @ 126782646 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 126782646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_test_vectors_shake_256.68679953339180929325145666323094076011149046351879194926446411160558134348114
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @ 397059369 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 397059369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

... and 2 more tests.

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 3.kmac_stress_all_with_rand_reset.37136988953591040333409376480311872966609903300438351790644064089447944435422
    Line 2536, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37470150019 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 37470150019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.kmac_stress_all_with_rand_reset.91455720606741796644764354199151471709898471387135419906544471883248643432027
    Line 311, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 480079687 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 480079687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_stress_all has 1 failures.

18.kmac_stress_all.94981360239524906156860038993256318550133912588135497833116423873700546316899
Line 1013, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all/latest/run.log

  UVM_FATAL @ 32464210757 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (171 [0xab] vs 186 [0xba]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 32464210757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

36.kmac_entropy_refresh.51342849048932510868640565261954050945496725356242104122987900273606864244130
Line 325, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 1550791126 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (196 [0xc4] vs 184 [0xb8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1550791126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

38.kmac_app.87389154917700600923244684340120756119358458664345422069080552888061528581644
Line 547, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_app/latest/run.log

  UVM_FATAL @ 6317797227 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (54 [0x36] vs 6 [0x6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6317797227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.kmac_app.32313656163738104052681451141593781751460402165199282844468202201753571366556
Line 325, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_app/latest/run.log

  UVM_FATAL @ 962103281 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (87 [0x57] vs 198 [0xc6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 962103281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 26.kmac_entropy_refresh.61424571046532751279554610416025783420967303996293107836320782502485074119902
    Line 1038, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 122173426618 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 122173426618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 38.kmac_stress_all.110993756967338038836428255552934232137596838956063317353990152314234715449932
    Line 988, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 22846529285 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 22846529285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_sideload has 1 failures.
  - 49.kmac_sideload.76408484521838954712268134369532222332864557406997532160642923008720084818736
    Line 1022, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```