0cdf265eaa| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.660m | 10.947ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.250s | 379.823us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.240s | 29.230us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 22.830s | 8.925ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 7.540s | 171.726us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.720s | 43.177us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.240s | 29.230us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 7.540s | 171.726us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.780s | 10.515us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.540s | 181.372us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 58.329m | 509.987ms | 49 | 50 | 98.00 |
| V2 | burst_write | kmac_burst_write | 26.257m | 15.461ms | 48 | 50 | 96.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 41.183m | 103.821ms | 48 | 50 | 96.00 |
| kmac_test_vectors_sha3_256 | 40.824m | 460.329ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_sha3_384 | 32.400m | 77.491ms | 48 | 50 | 96.00 | ||
| kmac_test_vectors_sha3_512 | 24.324m | 352.905ms | 48 | 50 | 96.00 | ||
| kmac_test_vectors_shake_128 | 1.928h | 2.970s | 48 | 50 | 96.00 | ||
| kmac_test_vectors_shake_256 | 1.591h | 1.427s | 48 | 50 | 96.00 | ||
| kmac_test_vectors_kmac | 7.300s | 4.054ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac_xof | 8.280s | 2.039ms | 48 | 50 | 96.00 | ||
| V2 | sideload | kmac_sideload | 8.605m | 24.270ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 6.372m | 27.912ms | 47 | 50 | 94.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 7.581m | 62.092ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 7.670m | 39.844ms | 48 | 50 | 96.00 |
| V2 | error | kmac_error | 8.675m | 82.861ms | 48 | 50 | 96.00 |
| V2 | key_error | kmac_key_error | 8.780s | 2.967ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 50.850s | 1.699ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 37.590s | 7.309ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.060m | 6.114ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 51.260s | 1.412ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 44.396m | 36.614ms | 43 | 50 | 86.00 |
| V2 | intr_test | kmac_intr_test | 0.860s | 15.489us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.910s | 256.184us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.190s | 254.784us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.190s | 254.784us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.250s | 379.823us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.240s | 29.230us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 7.540s | 171.726us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.830s | 383.072us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.250s | 379.823us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.240s | 29.230us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 7.540s | 171.726us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.830s | 383.072us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1019 | 1050 | 97.05 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.460s | 605.264us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.460s | 605.264us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.460s | 605.264us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.460s | 605.264us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.390s | 130.283us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 2.199m | 18.122ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.680s | 315.382us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.680s | 315.382us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 51.260s | 1.412ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.660m | 10.947ms | 49 | 50 | 98.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.605m | 24.270ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.460s | 605.264us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 2.199m | 18.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 2.199m | 18.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 2.199m | 18.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.660m | 10.947ms | 49 | 50 | 98.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 51.260s | 1.412ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 2.199m | 18.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 8.071m | 14.643ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.660m | 10.947ms | 49 | 50 | 98.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.056h | 157.869ms | 10 | 50 | 20.00 |
| V3 | TOTAL | 10 | 50 | 20.00 | |||
| TOTAL | 1218 | 1290 | 94.42 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 25 | 25 | 11 | 44.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.10 | 98.10 | 92.66 | 99.89 | 96.36 | 95.91 | 98.89 | 97.89 |
UVM_ERROR (cip_base_vseq.sv:815) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
0.kmac_stress_all_with_rand_reset.10302379666203041101665064357676700972334144830342450023983588435456369297648
Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7955554255 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7955554255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_stress_all_with_rand_reset.2929199553885836292144597294814129255825330251627727875020293796760468901981
Line 613, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15173696088 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15173696088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 15 failures:
Test kmac_test_vectors_shake_256 has 2 failures.
5.kmac_test_vectors_shake_256.26509802386886227103403060399606697915958107477732694728954918187820370841260
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 20795247 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 20795247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.kmac_test_vectors_shake_256.72762192032848626486632896642544616611176921464910135335605263932652504923151
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 49094350 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 49094350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_224 has 2 failures.
8.kmac_test_vectors_sha3_224.43612877126280261497543686471731303535190832310419010386640191608543832223123
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_sha3_224/latest/run.log
UVM_ERROR @ 43010356 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 43010356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.kmac_test_vectors_sha3_224.97760933151536529696653708164643013215063833810670957490047287039756846756960
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_sha3_224/latest/run.log
UVM_ERROR @ 17977112 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 17977112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
12.kmac_stress_all.84626883167424901398676882498525457998593101685991190658549126102058121242594
Line 917, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all/latest/run.log
UVM_ERROR @ 35556963564 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 35556963564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_384 has 2 failures.
16.kmac_test_vectors_sha3_384.105593458675606184978979111699676414512998882068693124564612264901635442920402
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_sha3_384/latest/run.log
UVM_ERROR @ 20463954 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 20463954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.kmac_test_vectors_sha3_384.22404515532769046266855644004537379948749094843161344141190794053832558982666
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_sha3_384/latest/run.log
UVM_ERROR @ 59946804 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 59946804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_512 has 2 failures.
29.kmac_test_vectors_sha3_512.12406924209801701072237111791455906142621395405717420496272045342276026582873
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_sha3_512/latest/run.log
UVM_ERROR @ 42806645 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 42806645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.kmac_test_vectors_sha3_512.12771548128199453877201250934849544417472793405129770115477495265306525958012
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_sha3_512/latest/run.log
UVM_ERROR @ 55845096 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 55845096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more tests.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 10 failures:
1.kmac_stress_all_with_rand_reset.71966047182686581686719718322578001508195795174066265609098326655259452026577
Line 1036, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 69577984779 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
UVM_INFO @ 69577984779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.kmac_stress_all_with_rand_reset.4863694898177521140537032798165697719974661294512661642428804232866910527125
Line 1111, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38362189686 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
UVM_INFO @ 38362189686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 7 failures:
2.kmac_stress_all.22232455553061862095423707036776460977830240842524145781082752848682208786854
Line 1584, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all/latest/run.log
UVM_FATAL @ 935420379263 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 935420379263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.kmac_stress_all.42758206402224523511486496855095761954531879186381874428689098996261666655014
Line 1212, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log
UVM_FATAL @ 218519092746 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 218519092746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
9.kmac_stress_all_with_rand_reset.107953912048171925730065802939802815991593961473225874474578285442240200460647
Line 313, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11878805649 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 11878805649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.kmac_stress_all_with_rand_reset.45943141008869126814578505150252703066799232902598228365123027669679246178528
Line 1431, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 612413783805 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 612413783805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
44.kmac_error.52780633638909603406095593629635123864179013483600636625856996748019436423015
Line 987, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_error/latest/run.log
UVM_FATAL @ 10038561720 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10038561720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 7 failures:
6.kmac_stress_all.29902181337749002642023300313701271237844712303688244680754126380677107425844
Line 901, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all/latest/run.log
UVM_FATAL @ 109260601870 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (43 [0x2b] vs 65 [0x41]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 109260601870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.kmac_stress_all.72568943976929820646339688685053578193414944704718070898291200533089658382547
Line 295, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_stress_all/latest/run.log
UVM_FATAL @ 647797741 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (251 [0xfb] vs 176 [0xb0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 647797741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
25.kmac_app.10313961517192225856620131450332758541340577328882198314743293585612566027514
Line 473, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_app/latest/run.log
UVM_FATAL @ 10794763774 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (66 [0x42] vs 167 [0xa7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 10794763774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.kmac_app.36691890032516783817715876502204203279048386985524137703178660062604116185562
Line 375, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_app/latest/run.log
UVM_FATAL @ 1864416692 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (206 [0xce] vs 231 [0xe7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 1864416692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
41.kmac_entropy_refresh.85119689859913303898459507995869623816823251184325702686916812663947139114045
Line 415, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 7400999504 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (244 [0xf4] vs 15 [0xf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 7400999504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
Test kmac_burst_write has 2 failures.
3.kmac_burst_write.91848326855566270570752847976505803018384044349861700175373594600413732284326
Line 1010, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.kmac_burst_write.44294196074096314927727885698318924958123089342918503709417557943791420478755
Line 764, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 1 failures.
17.kmac_error.88795967929145397512781169155641678973630544960936077990743835153487723428553
Line 796, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
37.kmac_entropy_refresh.35275534385222050954446011333079190179299225876814973143422491109934153177687
Line 1078, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
Test kmac_long_msg_and_output has 1 failures.
21.kmac_long_msg_and_output.24818717374128292989646787070467579479974835687793275777019625841314356262001
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest/run.log
Job ID: smart:daa4eade-cab6-4721-8800-c36641ff0489
Test kmac_test_vectors_shake_128 has 1 failures.
44.kmac_test_vectors_shake_128.9084509660136184410499682603722231839505921991881733906583405217849309249292
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_shake_128/latest/run.log
Job ID: smart:1b4c1873-0e2f-4402-bc61-7df8f0121c5e