KMAC/MASKED Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.590m	4.890ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	122.064us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	58.424us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.840s	5.546ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.770s	381.924us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.790s	77.741us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	58.424us	20	20	100.00
		kmac_csr_aliasing	9.770s	381.924us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	36.989us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	155.811us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	57.432m	96.857ms	50	50	100.00
V2	burst_write	kmac_burst_write	28.086m	16.626ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.959m	966.855ms	50	50	100.00
		kmac_test_vectors_sha3_256	40.353m	494.626ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.849m	446.552ms	49	50	98.00
		kmac_test_vectors_sha3_512	24.287m	213.397ms	50	50	100.00
		kmac_test_vectors_shake_128	1.851h	1.034s	50	50	100.00
		kmac_test_vectors_shake_256	1.696h	3.134s	50	50	100.00
		kmac_test_vectors_kmac	7.900s	585.791us	50	50	100.00
		kmac_test_vectors_kmac_xof	9.190s	1.446ms	50	50	100.00
V2	sideload	kmac_sideload	8.325m	15.108ms	50	50	100.00
V2	app	kmac_app	7.184m	26.386ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.834m	50.962ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.635m	36.710ms	49	50	98.00
V2	error	kmac_error	8.258m	29.120ms	48	50	96.00
V2	key_error	kmac_key_error	7.850s	8.934ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.048m	2.537ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	25.160s	714.786us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.168m	40.250ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	55.480s	1.877ms	50	50	100.00
V2	stress_all	kmac_stress_all	59.681m	139.242ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.880s	99.387us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	145.521us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.430s	192.862us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.430s	192.862us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	122.064us	5	5	100.00
		kmac_csr_rw	1.210s	58.424us	20	20	100.00
		kmac_csr_aliasing	9.770s	381.924us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	469.411us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	122.064us	5	5	100.00
		kmac_csr_rw	1.210s	58.424us	20	20	100.00
		kmac_csr_aliasing	9.770s	381.924us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	469.411us	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.450s	47.626us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.450s	47.626us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.450s	47.626us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.450s	47.626us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.210s	1.034ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.683m	37.289ms	5	5	100.00
		kmac_tl_intg_err	5.190s	918.480us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.190s	918.480us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	55.480s	1.877ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.590m	4.890ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.325m	15.108ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.450s	47.626us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.683m	37.289ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.683m	37.289ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.683m	37.289ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.590m	4.890ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	55.480s	1.877ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.683m	37.289ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.473m	13.468ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.590m	4.890ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	55.784m	310.022ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			1248	1290	96.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.82	98.10	92.49	99.89	94.55	95.91	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test kmac_stress_all_with_rand_reset has 24 failures.
  - 4.kmac_stress_all_with_rand_reset.64967571426042017457400892802130844354609966874155736121645858059308000268146
    Line 274, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7650893819 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7650893819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.94369085655571426192025083561668486894576053000749849464410689087688576540061
    Line 643, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57082917803 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 57082917803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 2.kmac_stress_all_with_rand_reset.51985650261356773392596030606101372860337499462899861825896247062427405065558
    Line 714, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37012672550 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 37012672550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.42367166674979903387420625561799651111519106784708924581120330253589489260060
    Line 2216, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 204469740366 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 204469740366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app has 2 failures.

15.kmac_app.90647866290310369955555380821488952699449376491850767879548458951848919490329
Line 869, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_app/latest/run.log

  UVM_FATAL @ 4438150182 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (148 [0x94] vs 120 [0x78]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4438150182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.kmac_app.38646472483280873179730770430384589305180294794666516092792067995986368837127
Line 755, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_app/latest/run.log

  UVM_FATAL @ 29043936009 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (45 [0x2d] vs 116 [0x74]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 29043936009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

18.kmac_entropy_refresh.96672175254076525616176809293583335939209957814479792187540526041705280827348
Line 673, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3630554985 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (79 [0x4f] vs 13 [0xd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3630554985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

27.kmac_stress_all.111057338365098175743927954873394503322982688903566117842065940355116743399440
Line 661, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all/latest/run.log

  UVM_FATAL @ 2737008694 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (212 [0xd4] vs 110 [0x6e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2737008694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

42.kmac_stress_all_with_rand_reset.76262728828234195499785840926596151212422924953155109699434660936915201738738
Line 845, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 5374864841 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (114 [0x72] vs 134 [0x86]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5374864841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_error has 2 failures.
  - 0.kmac_error.32812244634111301343880260794040451810865013300856887100223421359170495797197
    Line 293, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_error/latest/run.log
```
  UVM_FATAL @ 11611735489 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 11611735489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.kmac_error.70427244758371292699460009451278162097484536352444013625984958283922716539715
    Line 323, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_error/latest/run.log
```
  UVM_FATAL @ 10497696200 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10497696200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 21.kmac_stress_all_with_rand_reset.5419291001452953010686058024505573497936409292129777566643690952164799061826
    Line 1136, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 96413051749 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 96413051749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 4.kmac_test_vectors_sha3_384.28073699307504726085320670034586082121528587499259646420928170261120265123687
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @ 133055627 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 133055627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_smoke has 1 failures.
  - 28.kmac_smoke.95043651995537990887818699474290609173757411339796008213822126038299885481796
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_smoke/latest/run.log
```
  UVM_ERROR @ 182815683 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 182815683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 43.kmac_burst_write.56493207644069075570262679948869019582411495474488247749184694871441935353806
    Line 602, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```