KMAC/MASKED Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.672m	8.388ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.230s	31.458us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.290s	523.545us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.210s	1.448ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	12.000s	6.486ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.810s	394.409us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.290s	523.545us	20	20	100.00
		kmac_csr_aliasing	12.000s	6.486ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.830s	122.243us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.630s	171.493us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.138m	446.863ms	50	50	100.00
V2	burst_write	kmac_burst_write	29.923m	15.053ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.083m	102.356ms	50	50	100.00
		kmac_test_vectors_sha3_256	49.655m	1.855s	49	50	98.00
		kmac_test_vectors_sha3_384	32.230m	291.621ms	50	50	100.00
		kmac_test_vectors_sha3_512	22.977m	52.391ms	50	50	100.00
		kmac_test_vectors_shake_128	1.981h	2.384s	50	50	100.00
		kmac_test_vectors_shake_256	1.549h	911.819ms	50	50	100.00
		kmac_test_vectors_kmac	7.550s	640.284us	48	50	96.00
		kmac_test_vectors_kmac_xof	8.620s	952.955us	50	50	100.00
V2	sideload	kmac_sideload	9.861m	183.479ms	49	50	98.00
V2	app	kmac_app	7.027m	24.828ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.984m	55.722ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.500m	81.125ms	50	50	100.00
V2	error	kmac_error	8.038m	23.733ms	48	50	96.00
V2	key_error	kmac_key_error	8.000s	6.236ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.110s	1.864ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.410s	1.803ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.249m	22.566ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.247m	1.049ms	50	50	100.00
V2	stress_all	kmac_stress_all	52.307m	78.652ms	45	50	90.00
V2	intr_test	kmac_intr_test	0.890s	146.495us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	20.918us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.730s	141.207us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.730s	141.207us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.230s	31.458us	5	5	100.00
		kmac_csr_rw	1.290s	523.545us	20	20	100.00
		kmac_csr_aliasing	12.000s	6.486ms	5	5	100.00
		kmac_same_csr_outstanding	2.700s	994.279us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.230s	31.458us	5	5	100.00
		kmac_csr_rw	1.290s	523.545us	20	20	100.00
		kmac_csr_aliasing	12.000s	6.486ms	5	5	100.00
		kmac_same_csr_outstanding	2.700s	994.279us	20	20	100.00
V2		TOTAL			1037	1050	98.76
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	32.429us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	32.429us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	32.429us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	32.429us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.040s	515.325us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.909m	8.143ms	5	5	100.00
		kmac_tl_intg_err	6.500s	2.993ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.500s	2.993ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.247m	1.049ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.672m	8.388ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.861m	183.479ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	32.429us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.909m	8.143ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.909m	8.143ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.909m	8.143ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.672m	8.388ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.247m	1.049ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.909m	8.143ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.065m	13.102ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.672m	8.388ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	44.003m	94.203ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			1244	1290	96.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.81	98.10	92.43	99.89	94.55	95.91	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test kmac_stress_all_with_rand_reset has 26 failures.
  - 0.kmac_stress_all_with_rand_reset.18507681595592851189524029027779248154378617885190964792652748600138553851329
    Line 1253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 207449409849 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 207449409849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.100728160730689916604942626315271760749056273321800884630421441976741657644219
    Line 566, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13778103584 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13778103584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 5 failures:
- Test kmac_stress_all has 3 failures.
  - 0.kmac_stress_all.85036512170054251131293550150575652975121131678340943967693145405633468208673
    Line 1604, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 342508631729 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 342508631729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.kmac_stress_all.64975162974667598314770029354748134148157550315387548226047696623085168049189
    Line 558, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 74651351699 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 74651351699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 2.kmac_stress_all_with_rand_reset.110030932356257078635169331807537706853425825574994429062695255601056232723652
    Line 1920, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 310262210175 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 310262210175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 22.kmac_error.20837430961488020700405276565465893301504032780431535907679925996768541736720
    Line 806, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_error/latest/run.log
```
  UVM_FATAL @ 10089123369 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10089123369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_stress_all has 2 failures.

6.kmac_stress_all.22310588073457229772308757210752630604610424861475688882065592174591277757830
Line 1239, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all/latest/run.log

  UVM_FATAL @ 11765409061 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (51 [0x33] vs 232 [0xe8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11765409061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.kmac_stress_all.47235998245188319945567160324380691794686957379655906373008431208235229907014
Line 817, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all/latest/run.log

  UVM_FATAL @ 4861317623 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (1 [0x1] vs 245 [0xf5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4861317623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

14.kmac_app.110366085877370556283009931211019653519088008829438830463049738855120007933444
Line 381, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_app/latest/run.log

  UVM_FATAL @ 2594210858 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (240 [0xf0] vs 34 [0x22]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2594210858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_error has 1 failures.

24.kmac_error.70896974271473579677752536259483367509500431452676835328721104842239179513194
Line 1120, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_error/latest/run.log

  UVM_FATAL @ 53453201493 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (147 [0x93] vs 60 [0x3c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 53453201493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

24.kmac_stress_all_with_rand_reset.26271235682493468913454559688382622818320250234969757678868011054931325369002
Line 1775, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 15665747997 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (241 [0xf1] vs 255 [0xff]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 15665747997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 17.kmac_stress_all_with_rand_reset.8426501158008135106253629358543709676149052953539731683493766112055483110877
    Line 405, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14052580909 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 14052580909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.kmac_stress_all_with_rand_reset.45125987383800472938513727284486044234619717160206761599521868219032223053919
    Line 646, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5060352932 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 5060352932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_kmac has 2 failures.
  - 0.kmac_test_vectors_kmac.18537643049778039035997526033874768881209182127497086567310707397375327768188
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  90068972 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  90068972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.kmac_test_vectors_kmac.51414514487752117598210733275734959567203065741108695810942524485212834091015
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  50415585 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  50415585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 13.kmac_test_vectors_sha3_256.48433866264264924774028167059668350398970290120304198058419014176755402983887
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  76175945 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  76175945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 6.kmac_app_with_partial_data.110689023361389005522622789465942910078028452777054746038469591768461757788313
    Line 754, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_sideload has 1 failures.
  - 48.kmac_sideload.71806676414964431038981820520153038345348025236758169554829700321198511733006
    Line 1010, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```