KMAC/MASKED Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.377m	8.043ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	30.683us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.250s	101.419us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.200s	5.756ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.030s	539.969us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.620s	278.362us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.250s	101.419us	20	20	100.00
		kmac_csr_aliasing	10.030s	539.969us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	13.041us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	39.518us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	56.660m	275.009ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.754m	14.515ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.498m	1.081s	50	50	100.00
		kmac_test_vectors_sha3_256	37.218m	194.994ms	50	50	100.00
		kmac_test_vectors_sha3_384	31.674m	549.781ms	50	50	100.00
		kmac_test_vectors_sha3_512	22.532m	51.027ms	50	50	100.00
		kmac_test_vectors_shake_128	1.819h	2.555s	50	50	100.00
		kmac_test_vectors_shake_256	1.550h	2.747s	50	50	100.00
		kmac_test_vectors_kmac	8.760s	1.155ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.990s	664.584us	50	50	100.00
V2	sideload	kmac_sideload	7.946m	5.957ms	50	50	100.00
V2	app	kmac_app	6.392m	18.941ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.114m	16.783ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.112m	32.462ms	49	50	98.00
V2	error	kmac_error	8.005m	45.765ms	49	50	98.00
V2	key_error	kmac_key_error	7.530s	4.842ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	54.150s	4.357ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.840s	1.219ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.248m	28.302ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	39.630s	3.511ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.353m	60.859ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.850s	59.212us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	36.379us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.810s	145.941us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.810s	145.941us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	30.683us	5	5	100.00
		kmac_csr_rw	1.250s	101.419us	20	20	100.00
		kmac_csr_aliasing	10.030s	539.969us	5	5	100.00
		kmac_same_csr_outstanding	2.660s	238.521us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	30.683us	5	5	100.00
		kmac_csr_rw	1.250s	101.419us	20	20	100.00
		kmac_csr_aliasing	10.030s	539.969us	5	5	100.00
		kmac_same_csr_outstanding	2.660s	238.521us	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	181.570us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	181.570us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	181.570us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	181.570us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.060s	526.046us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.679m	6.766ms	5	5	100.00
		kmac_tl_intg_err	5.110s	226.540us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.110s	226.540us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.630s	3.511ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.377m	8.043ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	7.946m	5.957ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	181.570us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.679m	6.766ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.679m	6.766ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.679m	6.766ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.377m	8.043ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.630s	3.511ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.679m	6.766ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.332m	48.665ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.377m	8.043ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	49.956m	605.097ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			1248	1290	96.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.86	98.10	92.71	99.89	94.55	95.97	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test kmac_stress_all_with_rand_reset has 26 failures.
  - 2.kmac_stress_all_with_rand_reset.21966147494345423686712644562269903670517066172337233837221519849524963937506
    Line 1109, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56853378604 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 56853378604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.58199750901694053629034883001888259281683709014217804242756550113156485432124
    Line 1425, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 91655244712 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 91655244712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.12231651128525365896735346139109176963451509986411664486741314759356451027932
    Line 1895, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108148061137 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 108148061137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.90072670820366052054867904889081697485723754879725027974278194766295724442916
    Line 283, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 164318428 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 164318428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_entropy_refresh has 1 failures.

7.kmac_entropy_refresh.11375865787469751811468470239530038966382265020635252831515928097682397208837
Line 563, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5464905730 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (55 [0x37] vs 130 [0x82]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5464905730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 3 failures.

7.kmac_stress_all.9814645211767007231518677485852683384970259190371249294742996541471783823546
Line 585, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all/latest/run.log

  UVM_FATAL @ 1852718121 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (18 [0x12] vs 21 [0x15]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1852718121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_stress_all.11192697935720206253951957916234908173490506837781939344108017975255171881751
Line 1945, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all/latest/run.log

  UVM_FATAL @ 132695157901 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (48 [0x30] vs 200 [0xc8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 132695157901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_app has 1 failures.

11.kmac_app.82018451632018715107112292256407108750139328887135617526849900943843229910476
Line 369, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_app/latest/run.log

  UVM_FATAL @ 1290875839 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (205 [0xcd] vs 47 [0x2f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1290875839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 10.kmac_stress_all_with_rand_reset.41857243046540874936536536615792687135485657527497887296503912206104900072429
    Line 1127, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 52849733891 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 52849733891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.kmac_stress_all_with_rand_reset.52164402613066096401082053747537014773354731562372333714511179557505464123163
    Line 748, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 16797731991 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 16797731991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 24.kmac_error.3510185944143995162858866917782549090152484947114513105026141074349231709952
    Line 657, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_error/latest/run.log
```
  UVM_FATAL @ 10021597316 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10021597316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_smoke has 1 failures.
  - 19.kmac_smoke.83753952936892563553518944661480168251799921712703452036027374407225983339776
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_smoke/latest/run.log
```
  UVM_ERROR @ 167340274 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 167340274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 29.kmac_stress_all.23752813928553691323082283269092891635000406660718980982863843787344297289247
    Line 633, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 34819638677 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 34819638677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 13.kmac_burst_write.70148495366398979427767094261193183194911341565984782734309059606837769136436
    Line 542, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```