KMAC/MASKED Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.448m	17.244ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.190s	113.122us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	33.654us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.210s	4.123ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.580s	2.061ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.720s	132.941us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	33.654us	20	20	100.00
		kmac_csr_aliasing	10.580s	2.061ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	14.254us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.250s	31.406us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	46.994m	108.227ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.596m	15.234ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.608m	979.907ms	50	50	100.00
		kmac_test_vectors_sha3_256	38.960m	509.717ms	50	50	100.00
		kmac_test_vectors_sha3_384	30.790m	1.004s	48	50	96.00
		kmac_test_vectors_sha3_512	22.637m	123.195ms	50	50	100.00
		kmac_test_vectors_shake_128	1.737h	1.048s	50	50	100.00
		kmac_test_vectors_shake_256	1.526h	821.500ms	50	50	100.00
		kmac_test_vectors_kmac	7.590s	842.750us	49	50	98.00
		kmac_test_vectors_kmac_xof	6.900s	301.046us	49	50	98.00
V2	sideload	kmac_sideload	8.580m	103.762ms	50	50	100.00
V2	app	kmac_app	6.585m	69.299ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.228m	7.328ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.204m	198.227ms	49	50	98.00
V2	error	kmac_error	7.315m	20.347ms	49	50	98.00
V2	key_error	kmac_key_error	8.790s	7.363ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	31.360s	1.469ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.780s	6.819ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.136m	7.645ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	58.080s	851.867us	50	50	100.00
V2	stress_all	kmac_stress_all	57.037m	70.980ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.890s	27.311us	50	50	100.00
V2	alert_test	kmac_alert_test	0.980s	29.882us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.140s	147.119us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.140s	147.119us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.190s	113.122us	5	5	100.00
		kmac_csr_rw	1.190s	33.654us	20	20	100.00
		kmac_csr_aliasing	10.580s	2.061ms	5	5	100.00
		kmac_same_csr_outstanding	2.470s	300.901us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.190s	113.122us	5	5	100.00
		kmac_csr_rw	1.190s	33.654us	20	20	100.00
		kmac_csr_aliasing	10.580s	2.061ms	5	5	100.00
		kmac_same_csr_outstanding	2.470s	300.901us	20	20	100.00
V2		TOTAL			1040	1050	99.05
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.720s	94.314us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.720s	94.314us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.720s	94.314us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.720s	94.314us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.930s	234.010us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.787m	14.505ms	5	5	100.00
		kmac_tl_intg_err	5.320s	293.002us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.320s	293.002us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	58.080s	851.867us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.448m	17.244ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.580m	103.762ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.720s	94.314us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.787m	14.505ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.787m	14.505ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.787m	14.505ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.448m	17.244ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	58.080s	851.867us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.787m	14.505ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.216m	55.436ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.448m	17.244ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	51.122m	502.311ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			1242	1290	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.12	98.10	92.74	99.86	96.36	95.97	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test kmac_stress_all_with_rand_reset has 29 failures.
  - 1.kmac_stress_all_with_rand_reset.8051771952249765308702726989271070336811864229099615602595208855598950894806
    Line 2108, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 125982388288 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 125982388288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.57210661127063008725388015501622049787963625406265979998261354926726862772148
    Line 1098, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 91276432469 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 91276432469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 3.kmac_stress_all_with_rand_reset.11978735824001061277015398649356979626836026791049743296803189920574610991462
    Line 542, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 131833300991 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 131833300991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.kmac_stress_all_with_rand_reset.16007903447645535410440689533509695289600222329262537642173067968394882618312
    Line 918, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 133488672864 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 133488672864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:

Test kmac_smoke has 1 failures.

12.kmac_smoke.76315854962225670870052207905562317444862232745089133150664667976847811777175
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_smoke/latest/run.log

  UVM_ERROR @ 115675361 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 115675361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_384 has 2 failures.

16.kmac_test_vectors_sha3_384.28592038348011028617726943948224351262338492441780775480888699323655563784712
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @ 187817231 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 187817231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.kmac_test_vectors_sha3_384.48842859778180386512828495960251102693388153531818559346267273103055920201139
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @ 158387888 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 158387888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_kmac has 1 failures.

18.kmac_test_vectors_kmac.61542752286466670071378462445916471456721614391394630278338421566278778292529
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @ 104585159 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 104585159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_kmac_xof has 1 failures.

34.kmac_test_vectors_kmac_xof.49274907370122438571254215555180856401126186460017104436075184902290466912897
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_kmac_xof/latest/run.log

  UVM_ERROR @  85153563 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  85153563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_entropy_refresh has 1 failures.

5.kmac_entropy_refresh.11834805388673910614458153186696835514304744586615268007062636133381920956884
Line 317, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2239071053 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (203 [0xcb] vs 253 [0xfd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2239071053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

34.kmac_app.24599794603184485166832612340614759071273583760143335315509781392702156476686
Line 997, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_app/latest/run.log

  UVM_FATAL @ 19066801881 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (248 [0xf8] vs 191 [0xbf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 19066801881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

34.kmac_stress_all_with_rand_reset.80928968631194541977726029644565334042334664902190655796744374225298102746289
Line 1190, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 212238154864 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (64 [0x40] vs 80 [0x50]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 212238154864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

44.kmac_stress_all.90669874924830991376110919688234640276285802935243917163743171224700520302741
Line 823, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_stress_all/latest/run.log

  UVM_FATAL @ 15490758407 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (111 [0x6f] vs 67 [0x43]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 15490758407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all has 2 failures.
  - 9.kmac_stress_all.97559480764709770662481575480924563276381978976905222297919170198169310022851
    Line 2473, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 141444913691 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 141444913691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.kmac_stress_all.39424012237706888228913170922306389798427806450495344767857044063888727526
    Line 2440, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 238202278202 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 238202278202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 42.kmac_stress_all_with_rand_reset.2307432876615731206268943499889252674331705264086340007503275959786384105504
    Line 1553, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 82672256657 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 82672256657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 43.kmac_error.108862427306960619768004635563510716000263457470436697543156263437622259761380
    Line 404, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_error/latest/run.log
```
  UVM_FATAL @ 10083334103 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10083334103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 14.kmac_stress_all_with_rand_reset.102466417305310608067230456959362200856950057486151251768537793040549792710177
    Line 323, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 471371463 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (49 [0x31] vs 25 [0x19]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 471371463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```