KMAC/MASKED Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.638m	23.407ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	53.187us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	41.079us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.710s	1.120ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.550s	3.760ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.790s	89.955us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	41.079us	20	20	100.00
		kmac_csr_aliasing	5.550s	3.760ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	48.492us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.520s	41.048us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	51.107m	344.778ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.976m	53.706ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	45.664m	1.374s	50	50	100.00
		kmac_test_vectors_sha3_256	39.926m	719.287ms	50	50	100.00
		kmac_test_vectors_sha3_384	32.666m	1.040s	50	50	100.00
		kmac_test_vectors_sha3_512	26.032m	618.114ms	49	50	98.00
		kmac_test_vectors_shake_128	1.946h	2.603s	50	50	100.00
		kmac_test_vectors_shake_256	1.774h	3.631s	48	50	96.00
		kmac_test_vectors_kmac	7.790s	422.493us	50	50	100.00
		kmac_test_vectors_kmac_xof	9.900s	1.502ms	50	50	100.00
V2	sideload	kmac_sideload	8.652m	110.188ms	50	50	100.00
V2	app	kmac_app	6.502m	16.975ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.640m	57.852ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.502m	112.479ms	49	50	98.00
V2	error	kmac_error	8.403m	18.163ms	49	50	98.00
V2	key_error	kmac_key_error	13.340s	1.810ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.320s	1.441ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.140s	8.629ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.086m	44.080ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	47.380s	3.000ms	49	50	98.00
V2	stress_all	kmac_stress_all	43.188m	299.129ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.890s	140.884us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	47.563us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.620s	1.044ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.620s	1.044ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	53.187us	5	5	100.00
		kmac_csr_rw	1.240s	41.079us	20	20	100.00
		kmac_csr_aliasing	5.550s	3.760ms	5	5	100.00
		kmac_same_csr_outstanding	2.830s	126.462us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	53.187us	5	5	100.00
		kmac_csr_rw	1.240s	41.079us	20	20	100.00
		kmac_csr_aliasing	5.550s	3.760ms	5	5	100.00
		kmac_same_csr_outstanding	2.830s	126.462us	20	20	100.00
V2		TOTAL			1040	1050	99.05
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.320s	57.860us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.320s	57.860us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.320s	57.860us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.320s	57.860us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.960s	101.462us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.916m	36.752ms	5	5	100.00
		kmac_tl_intg_err	5.510s	1.034ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.510s	1.034ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	47.380s	3.000ms	49	50	98.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.638m	23.407ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.652m	110.188ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.320s	57.860us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.916m	36.752ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.916m	36.752ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.916m	36.752ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.638m	23.407ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	47.380s	3.000ms	49	50	98.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.916m	36.752ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.466m	14.066ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.638m	23.407ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.818m	215.690ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1232	1250	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.25	97.91	92.65	99.89	76.76	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.54846278853497943922772314648008216983730728156978856669275675531572239611342
    Line 272, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3504371012 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3504371012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.54255672657261254788800587433805629177395610012961173769440104936192803713116
    Line 528, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20160467338 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20160467338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 4 failures:
- Test kmac_test_vectors_shake_256 has 2 failures.
  - 12.kmac_test_vectors_shake_256.39018271986320658940210401502979031964026163195338807728259418889138012365580
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  32136777 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  32136777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.kmac_test_vectors_shake_256.37748738705688735828126344531868836410476204279790498778068748841579400134851
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  79450384 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  79450384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_smoke has 1 failures.
  - 48.kmac_smoke.13247100152628172132071663521593362366774937534704099619230268285729507688763
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_smoke/latest/run.log
```
  UVM_ERROR @ 102785678 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 102785678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 49.kmac_test_vectors_sha3_512.2097031332942232660461036520658051690274475685855328378903796785170835080760
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @ 286237612 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 286237612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all has 3 failures.
  - 10.kmac_stress_all.98612540565079861916769069642709692079979839168465432090987306239780873893730
    Line 1470, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 491882042382 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 491882042382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.kmac_stress_all.16513380932547341691536931948602708863011748402303426323109405338693374513710
    Line 2582, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 232695814190 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 232695814190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 1 failures.

35.kmac_entropy_refresh.34287964355433524535661355431688199449313992503646821755437538960638633422253
Line 343, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3211977333 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (137 [0x89] vs 44 [0x2c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3211977333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_lc_escalation has 1 failures.

35.kmac_lc_escalation.63731543075823147873342294050795338075648026395500488217942309510235870906441
Line 288, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest/run.log

  UVM_FATAL @ 299625799 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (203 [0xcb] vs 144 [0x90]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 299625799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_error has 1 failures.

36.kmac_error.93702306379204360674742862752672380480922408544305680711215670909048015323681
Line 990, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_error/latest/run.log

  UVM_FATAL @ 4225555454 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (224 [0xe0] vs 140 [0x8c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4225555454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 2.kmac_stress_all_with_rand_reset.93273360059093681664611091163076473447510367937084439782065006508357464647285
    Line 262, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  83791382 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @  83791382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 47.kmac_burst_write.82870009145785465512683435268850567197552532126970924702933831614112912423540
    Line 705, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```