KMAC/MASKED Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.613m	18.759ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	82.454us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	30.715us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.220s	4.006ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.520s	2.083ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.710s	353.191us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	30.715us	20	20	100.00
		kmac_csr_aliasing	9.520s	2.083ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	100.272us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	138.469us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	53.631m	28.403ms	50	50	100.00
V2	burst_write	kmac_burst_write	28.827m	59.439ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.748m	394.487ms	50	50	100.00
		kmac_test_vectors_sha3_256	39.412m	997.110ms	49	50	98.00
		kmac_test_vectors_sha3_384	30.398m	66.708ms	49	50	98.00
		kmac_test_vectors_sha3_512	23.618m	98.757ms	48	50	96.00
		kmac_test_vectors_shake_128	1.769h	1.517s	49	50	98.00
		kmac_test_vectors_shake_256	1.657h	2.426s	50	50	100.00
		kmac_test_vectors_kmac	8.450s	4.779ms	49	50	98.00
		kmac_test_vectors_kmac_xof	7.650s	2.619ms	49	50	98.00
V2	sideload	kmac_sideload	9.307m	21.202ms	50	50	100.00
V2	app	kmac_app	6.908m	188.221ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.844m	200.000ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.727m	15.252ms	47	50	94.00
V2	error	kmac_error	9.936m	107.697ms	49	50	98.00
V2	key_error	kmac_key_error	14.760s	1.846ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.190s	1.624ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.520s	1.720ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.668m	100.947ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.129m	2.443ms	49	50	98.00
V2	stress_all	kmac_stress_all	38.657m	90.719ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	14.758us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	60.285us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.590s	139.707us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.590s	139.707us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	82.454us	5	5	100.00
		kmac_csr_rw	1.190s	30.715us	20	20	100.00
		kmac_csr_aliasing	9.520s	2.083ms	5	5	100.00
		kmac_same_csr_outstanding	2.600s	118.484us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	82.454us	5	5	100.00
		kmac_csr_rw	1.190s	30.715us	20	20	100.00
		kmac_csr_aliasing	9.520s	2.083ms	5	5	100.00
		kmac_same_csr_outstanding	2.600s	118.484us	20	20	100.00
V2		TOTAL			1034	1050	98.48
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	227.304us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	227.304us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	227.304us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	227.304us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.820s	249.016us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.701m	57.202ms	5	5	100.00
		kmac_tl_intg_err	5.240s	901.764us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.240s	901.764us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.129m	2.443ms	49	50	98.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.613m	18.759ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.307m	21.202ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	227.304us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.701m	57.202ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.701m	57.202ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.701m	57.202ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.613m	18.759ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.129m	2.443ms	49	50	98.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.701m	57.202ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.706m	32.587ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.613m	18.759ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	25.025m	18.211ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1226	1250	98.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	13	52.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.10	97.89	92.58	99.89	76.06	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.103771604472877431844890285251035658821406947967424635107135130138856966367704
    Line 633, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56198958557 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 56198958557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.77588471167881565092018899535571206777987975905160468003966172322434059969150
    Line 661, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23016538236 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 23016538236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 8 failures:
- Test kmac_test_vectors_sha3_512 has 2 failures.
  - 1.kmac_test_vectors_sha3_512.3020299510594990358899443445712399731452484947191068632113822481345046012331
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @  37449912 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  37449912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.kmac_test_vectors_sha3_512.102963336628056926163735900093563481767203525253867996042101881086878958840975
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @ 237959019 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 237959019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 4.kmac_test_vectors_sha3_384.53626442778310793757087524879852014450927541665580084021938670106221028253158
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @ 150309324 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 150309324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 13.kmac_test_vectors_shake_128.54429665048549870119122067359165119333623681418578539378259945535767608318545
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  39448251 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  39448251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac has 1 failures.
  - 26.kmac_test_vectors_kmac.49518405144885519641320225696523971657099630468765126983844479374544760169590
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  42818551 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  42818551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac_xof has 1 failures.
  - 35.kmac_test_vectors_kmac_xof.29971416751195208901354303665316226555290694801160240335384721426520096355413
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @  42752461 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  42752461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 2 more tests.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_lc_escalation has 1 failures.

4.kmac_lc_escalation.89646961798314258053653823344369338434375655348708107652479813288950806906096
Line 266, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest/run.log

  UVM_FATAL @ 523500297 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (78 [0x4e] vs 15 [0xf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 523500297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

11.kmac_entropy_refresh.57680674040159452104358508903378930125506901844625701576393509198313149228797
Line 377, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2519717211 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (74 [0x4a] vs 58 [0x3a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2519717211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.kmac_entropy_refresh.99115200774315370890654419027594672719749732120098606934777329823862270441230
Line 539, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 12160895519 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (120 [0x78] vs 18 [0x12]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 12160895519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

13.kmac_app.115343690156596451469651559262279990298872640351529121570825195014546937305443
Line 539, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_app/latest/run.log

  UVM_FATAL @ 7827747740 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (8 [0x8] vs 128 [0x80]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7827747740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.kmac_app.50798320411918812119562697944074874613694878263467951225118205190277374164405
Line 299, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_app/latest/run.log

  UVM_FATAL @ 1689796854 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (186 [0xba] vs 140 [0x8c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1689796854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all has 1 failures.
  - 35.kmac_stress_all.39658821751605391559988317053422708496280284340644959415972578497951886208457
    Line 1327, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 293718679503 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 293718679503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 39.kmac_error.89629563892261830570385907802898461504857327148180766911084092766183728739625
    Line 762, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_error/latest/run.log
```
  UVM_FATAL @ 10089209766 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10089209766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 4.kmac_app_with_partial_data.8234946421788320420792381631968139940947685711401830009407919011832460785836
    Line 954, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```