KMAC/MASKED Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.530m	4.489ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	97.890us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	419.695us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.410s	1.090ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.030s	208.935us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.520s	248.481us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	419.695us	20	20	100.00
		kmac_csr_aliasing	5.030s	208.935us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	18.035us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.460s	83.108us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.710m	458.959ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.767m	60.955ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.109m	1.444s	50	50	100.00
		kmac_test_vectors_sha3_256	40.672m	199.222ms	49	50	98.00
		kmac_test_vectors_sha3_384	31.662m	141.553ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.797m	200.898ms	50	50	100.00
		kmac_test_vectors_shake_128	1.884h	1.509s	50	50	100.00
		kmac_test_vectors_shake_256	1.672h	1.374s	48	50	96.00
		kmac_test_vectors_kmac	7.530s	673.937us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.240s	295.942us	50	50	100.00
V2	sideload	kmac_sideload	9.265m	30.958ms	50	50	100.00
V2	app	kmac_app	6.944m	18.210ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.891m	8.409ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.737m	19.118ms	48	50	96.00
V2	error	kmac_error	9.566m	40.786ms	49	50	98.00
V2	key_error	kmac_key_error	14.190s	2.005ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.710s	3.081ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.960s	1.128ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.050m	24.288ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	41.140s	1.109ms	50	50	100.00
V2	stress_all	kmac_stress_all	41.331m	160.162ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.870s	22.660us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	21.192us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.790s	150.436us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.790s	150.436us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	97.890us	5	5	100.00
		kmac_csr_rw	1.240s	419.695us	20	20	100.00
		kmac_csr_aliasing	5.030s	208.935us	5	5	100.00
		kmac_same_csr_outstanding	2.620s	116.365us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	97.890us	5	5	100.00
		kmac_csr_rw	1.240s	419.695us	20	20	100.00
		kmac_csr_aliasing	5.030s	208.935us	5	5	100.00
		kmac_same_csr_outstanding	2.620s	116.365us	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.540s	201.301us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.540s	201.301us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.540s	201.301us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.540s	201.301us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.190s	125.536us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.891m	36.363ms	5	5	100.00
		kmac_tl_intg_err	5.210s	1.067ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.210s	1.067ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	41.140s	1.109ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.530m	4.489ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.265m	30.958ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.540s	201.301us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.891m	36.363ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.891m	36.363ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.891m	36.363ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.530m	4.489ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	41.140s	1.109ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.891m	36.363ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.192m	28.833ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.530m	4.489ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	44.735m	65.084ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			1236	1250	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.12	97.91	92.62	99.89	76.06	95.59	99.05	97.73

Failure Buckets

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 8.kmac_stress_all_with_rand_reset.6067759599130068887265790223588884155537874506746490052053294622757504915262
    Line 447, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12455787898 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 12455787898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 2 failures.
  - 24.kmac_stress_all.47947928051925866764255584777980887592379398011865619760498912150623739760451
    Line 1342, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 39635192034 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 39635192034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.kmac_stress_all.48506549215151389431386165847543742368840587047462310199154567954951546893946
    Line 1068, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 107954933907 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 107954933907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 28.kmac_error.76710366719943126572194177214227960447593232418109099607872833869597826122819
    Line 791, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_error/latest/run.log
```
  UVM_FATAL @ 10107618491 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10107618491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_mubi has 1 failures.

0.kmac_mubi.107994158546071871944492720978305038740902246086497696930289359070252579763499
Line 921, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_mubi/latest/run.log

  UVM_FATAL @ 51565072549 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (145 [0x91] vs 115 [0x73]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 51565072549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

10.kmac_entropy_refresh.52310379666068007829165023467084442247736654504331010725824104693267543873106
Line 905, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 10416588092 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (227 [0xe3] vs 178 [0xb2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10416588092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.kmac_entropy_refresh.83857323456653447124187886404549649894267682508188091096212090985790776478549
Line 381, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 1665331507 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (244 [0xf4] vs 252 [0xfc]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1665331507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_shake_256 has 2 failures.
  - 6.kmac_test_vectors_shake_256.57261235340116059544358902731266386290926673746303733445035654758654968176732
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  92112711 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  92112711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.kmac_test_vectors_shake_256.106934783453072543363286994837442971293591175719167644394655653024954335702131
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  33937760 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  33937760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 16.kmac_test_vectors_sha3_256.34926315383016751517130384008229323213062632802072001953390949370385114737487
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  19848928 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  19848928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 0.kmac_stress_all_with_rand_reset.45805825232637133343575832285639252120298812396132419122761484358673551671203
    Line 1763, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 183694223738 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 183694223738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.17952504862885804033946985951245155802353978033761772384362197338046967368012
    Line 1624, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 132665300456 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 132665300456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 1.kmac_stress_all_with_rand_reset.29561327895811220840795049719855486455288111526190432037613354525581158565070
    Line 828, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 40733993601 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 40733993601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 44.kmac_burst_write.100257627086544537805082071914475162307565451760699599062875516719530473878696
    Line 723, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```