KMAC/MASKED Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.692m	20.027ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	18.182us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.280s	42.999us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.990s	2.487ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.480s	397.825us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.570s	350.158us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.280s	42.999us	20	20	100.00
		kmac_csr_aliasing	9.480s	397.825us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	18.305us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.390s	99.995us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	54.927m	739.564ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.536m	58.944ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.097m	807.999ms	50	50	100.00
		kmac_test_vectors_sha3_256	39.382m	484.938ms	49	50	98.00
		kmac_test_vectors_sha3_384	32.660m	92.546ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.426m	52.452ms	50	50	100.00
		kmac_test_vectors_shake_128	1.901h	926.394ms	50	50	100.00
		kmac_test_vectors_shake_256	1.546h	1.077s	50	50	100.00
		kmac_test_vectors_kmac	7.460s	1.004ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.020s	933.010us	50	50	100.00
V2	sideload	kmac_sideload	8.706m	87.125ms	50	50	100.00
V2	app	kmac_app	7.311m	104.209ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.595m	67.043ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.569m	26.666ms	48	50	96.00
V2	error	kmac_error	9.261m	63.150ms	50	50	100.00
V2	key_error	kmac_key_error	13.820s	6.680ms	48	50	96.00
V2	edn_timeout_error	kmac_edn_timeout_error	54.260s	2.322ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.180s	473.556us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.304m	19.677ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	25.790s	735.806us	50	50	100.00
V2	stress_all	kmac_stress_all	1.062h	261.630ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.880s	21.547us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	80.488us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.270s	235.230us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.270s	235.230us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	18.182us	5	5	100.00
		kmac_csr_rw	1.280s	42.999us	20	20	100.00
		kmac_csr_aliasing	9.480s	397.825us	5	5	100.00
		kmac_same_csr_outstanding	2.850s	149.695us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	18.182us	5	5	100.00
		kmac_csr_rw	1.280s	42.999us	20	20	100.00
		kmac_csr_aliasing	9.480s	397.825us	5	5	100.00
		kmac_same_csr_outstanding	2.850s	149.695us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.420s	394.417us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.420s	394.417us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.420s	394.417us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.420s	394.417us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.090s	220.862us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.830m	17.108ms	5	5	100.00
		kmac_tl_intg_err	4.910s	664.913us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.910s	664.913us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	25.790s	735.806us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.692m	20.027ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.706m	87.125ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.420s	394.417us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.830m	17.108ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.830m	17.108ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.830m	17.108ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.692m	20.027ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	25.790s	735.806us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.830m	17.108ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.583m	95.240ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.692m	20.027ms	49	50	98.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	30.714m	396.157ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1234	1250	98.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	20	80.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.55	99.89	76.76	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 2.kmac_stress_all_with_rand_reset.34534456551505481086755061408823976291718828078998391432282292450135523322795
    Line 648, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16825888999 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16825888999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.104322009226373304700289010206020393408214149188433556080494727386048128296572
    Line 285, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2225300001 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2225300001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_entropy_refresh has 2 failures.

6.kmac_entropy_refresh.112897112848848664007714849004205782970287242869871035379356618215805500308705
Line 351, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2657325280 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (223 [0xdf] vs 225 [0xe1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2657325280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_entropy_refresh.69073035438358028176794733119469254525490939705228273500314956377896074130719
Line 737, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 11545706771 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (195 [0xc3] vs 21 [0x15]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11545706771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

9.kmac_mubi.52072428461109797901878738076059459218694826657066587004666578362894271373158
Line 903, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_mubi/latest/run.log

  UVM_FATAL @ 36635671438 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (160 [0xa0] vs 161 [0xa1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 36635671438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

25.kmac_app.42284378050350496397299082902136081656371137099414338217386484677600273135529
Line 577, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_app/latest/run.log

  UVM_FATAL @ 3131154615 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (36 [0x24] vs 113 [0x71]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3131154615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 0.kmac_stress_all_with_rand_reset.52257438265198322535488577954166784902033574690564900587469881682188923165596
    Line 260, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  71077333 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @  71077333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.24261817517673504604998519868822639568700350547709890892525367120006427356349
    Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 102327529 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 102327529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 2 failures:

Test kmac_key_error has 2 failures.

1.kmac_key_error.63369053439925102208122172821811429238610724394922700109225064207944514592247
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_key_error/latest/run.log

  UVM_ERROR @ 144370331 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 144370331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.kmac_key_error.32449877024011323028408332545948799570998431780183176754979842247476467158870
Line 273, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_key_error/latest/run.log

  UVM_ERROR @ 4124718525 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 4124718525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_smoke has 1 failures.
  - 8.kmac_smoke.58181887062146294578069729349816549389477716718269211285089719985646586296152
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_smoke/latest/run.log
```
  UVM_ERROR @ 114997297 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 114997297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 37.kmac_test_vectors_sha3_256.89452483301125061068134808800434290845390660435802541576401495583975834265064
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  32373874 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  32373874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 9.kmac_stress_all_with_rand_reset.47910557444037626360887984272556738286546630679692753670277168568063139576676
    Line 567, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 37163606388 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 37163606388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 23.kmac_stress_all.98174467452374699808207684883897830901313950184330442579774605097461657832860
    Line 512, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 66782705180 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 66782705180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```