KMAC/MASKED Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.505m	23.130ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	117.167us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	116.586us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	17.970s	1.011ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.810s	569.000us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.680s	642.835us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	116.586us	20	20	100.00
		kmac_csr_aliasing	7.810s	569.000us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	16.457us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.350s	32.990us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.838m	465.842ms	48	50	96.00
V2	burst_write	kmac_burst_write	29.918m	14.619ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.802m	429.272ms	49	50	98.00
		kmac_test_vectors_sha3_256	41.456m	97.264ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.122m	72.771ms	50	50	100.00
		kmac_test_vectors_sha3_512	24.925m	207.254ms	50	50	100.00
		kmac_test_vectors_shake_128	1.816h	1.986s	48	50	96.00
		kmac_test_vectors_shake_256	1.636h	1.583s	50	50	100.00
		kmac_test_vectors_kmac	7.280s	2.847ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.760s	1.947ms	50	50	100.00
V2	sideload	kmac_sideload	9.513m	88.530ms	50	50	100.00
V2	app	kmac_app	7.199m	200.000ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.228m	13.856ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.086m	40.580ms	49	50	98.00
V2	error	kmac_error	9.310m	76.660ms	49	50	98.00
V2	key_error	kmac_key_error	13.880s	3.555ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	56.880s	1.857ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.610s	10.852ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.583m	23.470ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	30.840s	8.380ms	50	50	100.00
V2	stress_all	kmac_stress_all	41.641m	112.573ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.880s	39.244us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	167.361us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.120s	121.534us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.120s	121.534us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	117.167us	5	5	100.00
		kmac_csr_rw	1.200s	116.586us	20	20	100.00
		kmac_csr_aliasing	7.810s	569.000us	5	5	100.00
		kmac_same_csr_outstanding	2.650s	144.454us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	117.167us	5	5	100.00
		kmac_csr_rw	1.200s	116.586us	20	20	100.00
		kmac_csr_aliasing	7.810s	569.000us	5	5	100.00
		kmac_same_csr_outstanding	2.650s	144.454us	20	20	100.00
V2		TOTAL			1039	1050	98.95
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.540s	55.111us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.540s	55.111us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.540s	55.111us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.540s	55.111us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.240s	1.156ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.181m	12.933ms	5	5	100.00
		kmac_tl_intg_err	5.520s	2.639ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.520s	2.639ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	30.840s	8.380ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.505m	23.130ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.513m	88.530ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.540s	55.111us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.181m	12.933ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.181m	12.933ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.181m	12.933ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.505m	23.130ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	30.840s	8.380ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.181m	12.933ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.541m	6.106ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.505m	23.130ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	42.184m	429.073ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1233	1250	98.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.14	97.91	92.62	99.89	76.06	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 2.kmac_stress_all_with_rand_reset.114791327979079299555133429166957535528486034709050501627873022825005557313932
    Line 1356, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 102534222037 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 102534222037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.73982100361385554127413203748689331087194099913434332050151933678995222473479
    Line 1048, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 146420558006 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 146420558006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all has 3 failures.
  - 0.kmac_stress_all.41361307568867657908916991603705899278315801508576895605567561716017674051808
    Line 1868, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 241766986820 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 241766986820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.kmac_stress_all.71185380669429742510982405271466002796467233710331948137430586373702221816708
    Line 1520, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 28565433057 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 28565433057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 7.kmac_stress_all_with_rand_reset.19173656077872822717314703898860882135092363227262617071494265749363180148140
    Line 1003, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 28634506960 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 28634506960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 4 failures:
- Test kmac_error has 1 failures.
  - 14.kmac_error.56095751003254962752877809553675064889313317559782078764614026662873521382189
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_error/latest/run.log
```
  UVM_ERROR @  37986610 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  37986610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 20.kmac_test_vectors_sha3_224.86685056666698009127608690574318073258486002840325639022589936289189148891359
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  46632697 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  46632697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 2 failures.
  - 22.kmac_test_vectors_shake_128.25968954836974881547038280319908531463904372505254790527661217842856330005665
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  54508483 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  54508483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.kmac_test_vectors_shake_128.115664125779358830605557257179466693340288984598009048276459216363555466782436
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  61592966 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  61592966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test kmac_long_msg_and_output has 2 failures.
  - 29.kmac_long_msg_and_output.82974693395446181265624734897277533946558276605353724737688087876773234555051
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:c5e73d01-e56d-4fad-9536-f6cdae0f6f8b
```
  - 41.kmac_long_msg_and_output.19854610717176958532034325589222212295354621513749057549347562780226625856761
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:2459a8e8-edc2-485b-a6f9-4ebbde6a8f90
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 12.kmac_entropy_refresh.81178499957932871799976078499249683013713394057033678285547284942513102221221
    Line 591, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 13856776384 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (169 [0xa9] vs 43 [0x2b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13856776384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_app has 1 failures.
  - 48.kmac_app.103688688942965486569235948343923509649673967638032660795140506514248277633543
    Line 1112, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/MASKED Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9edf84e236`