KMAC/MASKED Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.450m	20.005ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	190.118us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.290s	27.251us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.070s	291.888us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.750s	1.608ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.920s	42.472us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.290s	27.251us	20	20	100.00
		kmac_csr_aliasing	9.750s	1.608ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	71.796us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.410s	150.265us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	52.602m	224.035ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.135m	57.380ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.257m	744.182ms	49	50	98.00
		kmac_test_vectors_sha3_256	43.752m	677.287ms	49	50	98.00
		kmac_test_vectors_sha3_384	32.247m	488.490ms	50	50	100.00
		kmac_test_vectors_sha3_512	22.965m	98.487ms	49	50	98.00
		kmac_test_vectors_shake_128	1.981h	3.802s	50	50	100.00
		kmac_test_vectors_shake_256	1.508h	949.805ms	50	50	100.00
		kmac_test_vectors_kmac	7.670s	2.111ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.490s	1.369ms	50	50	100.00
V2	sideload	kmac_sideload	10.426m	350.893ms	50	50	100.00
V2	app	kmac_app	6.325m	17.021ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.729m	20.450ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	8.062m	21.279ms	49	50	98.00
V2	error	kmac_error	8.112m	6.078ms	50	50	100.00
V2	key_error	kmac_key_error	14.390s	2.114ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.390s	1.878ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	24.210s	4.065ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.109m	61.449ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	41.980s	650.722us	50	50	100.00
V2	stress_all	kmac_stress_all	38.307m	23.559ms	45	50	90.00
V2	intr_test	kmac_intr_test	0.890s	15.685us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	20.466us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.320s	388.514us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.320s	388.514us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	190.118us	5	5	100.00
		kmac_csr_rw	1.290s	27.251us	20	20	100.00
		kmac_csr_aliasing	9.750s	1.608ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	791.673us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	190.118us	5	5	100.00
		kmac_csr_rw	1.290s	27.251us	20	20	100.00
		kmac_csr_aliasing	9.750s	1.608ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	791.673us	20	20	100.00
V2		TOTAL			1036	1050	98.67
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.490s	182.357us	15	20	75.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.490s	182.357us	15	20	75.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.490s	182.357us	15	20	75.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.490s	182.357us	15	20	75.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.020s	475.748us	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	1.954m	17.899ms	5	5	100.00
		kmac_tl_intg_err	5.780s	947.366us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.780s	947.366us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	41.980s	650.722us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.450m	20.005ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.426m	350.893ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.490s	182.357us	15	20	75.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.954m	17.899ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.954m	17.899ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.954m	17.899ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.450m	20.005ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	41.980s	650.722us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.954m	17.899ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.316m	59.193ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.450m	20.005ms	50	50	100.00
V2S		TOTAL			65	75	86.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	42.773m	64.475ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1217	1250	97.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.14	97.89	92.52	99.51	76.76	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 10 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

3.kmac_shadow_reg_errors_with_csr_rw.3289466281066323739589356774818108707061835675218371214360914766825499993424
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  51278705 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  51278705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.6018968093178081104684067423527183722766564058214817921235751855802822263912
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  42748944 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  42748944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_shadow_reg_errors has 5 failures.

8.kmac_shadow_reg_errors.39186658356088907914766279636369051259382766870766574965610447769956699860631
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  13070619 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  13070619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors.110040630275350705581789587935476588482439747270352862179314895146117604888867
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  10347949 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  10347949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.7501660652261802325878294535101392758130463913388122839657409961371181864581
    Line 631, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 76222160966 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 76222160966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.64699268826445392292286067464605069999967372972096379551948945915499290255642
    Line 3435, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64475224398 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 64475224398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 7 failures:

Test kmac_app has 3 failures.

5.kmac_app.73156417138181661178575019753500401613820232043943907193754118768589966955130
Line 573, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_app/latest/run.log

  UVM_FATAL @ 10661886167 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (113 [0x71] vs 255 [0xff]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10661886167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.kmac_app.28225650289864365723034489008590070057312725590007868516398088630550088127545
Line 531, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_app/latest/run.log

  UVM_FATAL @ 3953510619 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (223 [0xdf] vs 91 [0x5b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3953510619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_app_with_partial_data has 1 failures.

8.kmac_app_with_partial_data.67365661828100603286923474055734607237826347713386937190726958560144431466390
Line 577, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 9920813295 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (57 [0x39] vs 25 [0x19]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9920813295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

43.kmac_stress_all.54741095055830411048261980513719049514617506223972265529089837771655126240702
Line 273, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_stress_all/latest/run.log

  UVM_FATAL @ 329373820 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (36 [0x24] vs 220 [0xdc]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 329373820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.kmac_stress_all.58856467681668920382971663067250557157584375565795409491425821877375253366340
Line 379, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_stress_all/latest/run.log

  UVM_FATAL @ 5270842524 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (116 [0x74] vs 242 [0xf2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5270842524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

46.kmac_entropy_refresh.101234772143166215872236694219003282119134677428548920718724544475423239290179
Line 609, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5416068676 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (192 [0xc0] vs 99 [0x63]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5416068676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 3.kmac_stress_all_with_rand_reset.4002669843129551680567298213921399893213009394253770883840054834123717929379
    Line 1359, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 58168309547 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 58168309547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 3 failures.
  - 11.kmac_stress_all.99493976865748186264568845477453649268428800000175036720161295894761545483835
    Line 682, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 142313944372 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 142313944372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.kmac_stress_all.52540315382519757247555285092666831639987455270225971790152648535463204983652
    Line 482, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 10790459282 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10790459282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 15.kmac_test_vectors_sha3_512.90269651104524149489024878944762767783441285316785016827042680144053735912727
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @  45378434 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  45378434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 23.kmac_test_vectors_sha3_224.53339875181830628211107868336072212121840851338180824090576704498190211715951
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  50015435 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  50015435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 30.kmac_test_vectors_sha3_256.33954428603490727908603155931719675931129649424925181259679577098103725798883
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  29541433 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  29541433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 1.kmac_stress_all_with_rand_reset.79388492461721317231088539084295386196029006549427338393266283224281624732529
    Line 337, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 70893621297 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 70893621297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 23.kmac_burst_write.3981640462157202185487303963146446259976031385196825506385703049036631492343
    Line 596, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```