KMAC/MASKED Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.610m	17.703ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	57.728us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	127.129us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.360s	3.918ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.470s	494.627us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.440s	40.191us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	127.129us	20	20	100.00
		kmac_csr_aliasing	9.470s	494.627us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	12.737us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.530s	73.560us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.816m	128.233ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.835m	14.856ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.301m	1.093s	50	50	100.00
		kmac_test_vectors_sha3_256	42.962m	933.023ms	50	50	100.00
		kmac_test_vectors_sha3_384	32.125m	506.311ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.771m	614.303ms	50	50	100.00
		kmac_test_vectors_shake_128	1.854h	2.888s	50	50	100.00
		kmac_test_vectors_shake_256	1.578h	2.173s	49	50	98.00
		kmac_test_vectors_kmac	7.790s	658.238us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.490s	1.211ms	50	50	100.00
V2	sideload	kmac_sideload	8.965m	39.555ms	50	50	100.00
V2	app	kmac_app	6.312m	59.976ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.330m	80.841ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.278m	84.826ms	48	50	96.00
V2	error	kmac_error	8.239m	5.934ms	48	50	96.00
V2	key_error	kmac_key_error	12.540s	3.451ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.640s	1.769ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	17.060s	975.967us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.192m	11.289ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	41.530s	747.701us	50	50	100.00
V2	stress_all	kmac_stress_all	47.803m	125.283ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.900s	18.426us	50	50	100.00
V2	alert_test	kmac_alert_test	0.990s	154.045us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.250s	183.271us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.250s	183.271us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	57.728us	5	5	100.00
		kmac_csr_rw	1.210s	127.129us	20	20	100.00
		kmac_csr_aliasing	9.470s	494.627us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	1.255ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	57.728us	5	5	100.00
		kmac_csr_rw	1.210s	127.129us	20	20	100.00
		kmac_csr_aliasing	9.470s	494.627us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	1.255ms	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.500s	207.753us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.500s	207.753us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.500s	207.753us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.500s	207.753us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.730s	439.714us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.027m	33.122ms	5	5	100.00
		kmac_tl_intg_err	5.240s	893.653us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.240s	893.653us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	41.530s	747.701us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.610m	17.703ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.965m	39.555ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.500s	207.753us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.027m	33.122ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.027m	33.122ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.027m	33.122ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.610m	17.703ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	41.530s	747.701us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.027m	33.122ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.601m	11.840ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.610m	17.703ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	49.127m	286.272ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1234	1250	98.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.25	97.91	92.65	99.89	76.76	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 1.kmac_stress_all_with_rand_reset.38163861355621334732511128305942989518339511327015478404362192185556152250543
    Line 2223, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 391562796157 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 391562796157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.108679852286102897175876016325633577042102506314810732169463405087870253492854
    Line 535, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57004891380 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 57004891380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all has 2 failures.
  - 0.kmac_stress_all.18192712801270040481421822840054934601883730864766995440302875308204027824588
    Line 1272, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 33864674241 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 33864674241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.kmac_stress_all.52554115815910919498934707241915079512344925654687697308555224310410813730475
    Line 2322, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 167462520517 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 167462520517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 2 failures.
  - 8.kmac_error.51905581569724490983022216646890063425351732638663168907555117852120637604117
    Line 985, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_error/latest/run.log
```
  UVM_FATAL @ 10087618824 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10087618824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.kmac_error.25917997002927303348899407978602195002598519130156047452125874836293754975842
    Line 462, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_error/latest/run.log
```
  UVM_FATAL @ 10293909055 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10293909055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 0.kmac_stress_all_with_rand_reset.87176828086007103543390674330943609718716280714275734181132710835520436166787
    Line 1155, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 237609683655 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 237609683655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.11749905569370027157109260108364640586915267511842686846801464546560290320243
    Line 3690, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 286272072657 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 286272072657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 5.kmac_test_vectors_shake_256.82708061996552306479576058833153724144842439315516297185056999642253640608179
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  46531019 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  46531019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 21.kmac_stress_all.44031902091687090295179828640143557997937861549013385049419699098075995628852
    Line 494, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 6131377924 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 6131377924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_entropy_refresh has 2 failures.

5.kmac_entropy_refresh.60470280658399611827525201376216811822239686659626634876369753763048297261988
Line 467, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 11577135493 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (22 [0x16] vs 39 [0x27]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11577135493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.kmac_entropy_refresh.37432792670628099255377457861305820887154412336430479919425884335359083221892
Line 1001, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 13341006138 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (213 [0xd5] vs 187 [0xbb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13341006138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---