KMAC/MASKED Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.693m	4.723ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.190s	97.001us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	34.842us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.140s	1.522ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.640s	509.302us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.710s	438.377us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	34.842us	20	20	100.00
		kmac_csr_aliasing	9.640s	509.302us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	13.459us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	41.082us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.649m	276.443ms	48	50	96.00
V2	burst_write	kmac_burst_write	24.055m	200.000ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.472m	378.972ms	50	50	100.00
		kmac_test_vectors_sha3_256	42.604m	678.276ms	50	50	100.00
		kmac_test_vectors_sha3_384	30.904m	74.593ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.965m	850.267ms	50	50	100.00
		kmac_test_vectors_shake_128	1.900h	3.778s	49	50	98.00
		kmac_test_vectors_shake_256	1.848h	4.440s	50	50	100.00
		kmac_test_vectors_kmac	7.490s	482.146us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.010s	920.372us	49	50	98.00
V2	sideload	kmac_sideload	10.080m	414.233ms	50	50	100.00
V2	app	kmac_app	6.497m	5.233ms	45	50	90.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.468m	73.718ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.756m	29.319ms	49	50	98.00
V2	error	kmac_error	8.797m	78.869ms	50	50	100.00
V2	key_error	kmac_key_error	13.180s	3.300ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.850s	955.559us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.150s	702.577us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	59.570s	22.904ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.043m	3.875ms	50	50	100.00
V2	stress_all	kmac_stress_all	59.236m	385.837ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.910s	16.405us	50	50	100.00
V2	alert_test	kmac_alert_test	1.010s	213.503us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.100s	516.991us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.100s	516.991us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.190s	97.001us	5	5	100.00
		kmac_csr_rw	1.210s	34.842us	20	20	100.00
		kmac_csr_aliasing	9.640s	509.302us	5	5	100.00
		kmac_same_csr_outstanding	2.650s	985.199us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.190s	97.001us	5	5	100.00
		kmac_csr_rw	1.210s	34.842us	20	20	100.00
		kmac_csr_aliasing	9.640s	509.302us	5	5	100.00
		kmac_same_csr_outstanding	2.650s	985.199us	20	20	100.00
V2		TOTAL			1039	1050	98.95
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.540s	81.576us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.540s	81.576us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.540s	81.576us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.540s	81.576us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.060s	224.353us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.655m	6.756ms	5	5	100.00
		kmac_tl_intg_err	5.330s	224.015us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.330s	224.015us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.043m	3.875ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.693m	4.723ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.080m	414.233ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.540s	81.576us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.655m	6.756ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.655m	6.756ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.655m	6.756ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.693m	4.723ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.043m	3.875ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.655m	6.756ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.043m	20.081ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.693m	4.723ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	20.577m	15.132ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1233	1250	98.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.09	97.89	92.62	99.89	76.06	95.53	98.89	97.73

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.14669123069098488730264475295793320712202351172863058153056785643997480788333
    Line 813, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18516482681 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18516482681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.22398881854132024130001918369692801900058344228099068256669437953079465083806
    Line 891, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 82606714448 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 82606714448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 1 failures.
  - 1.kmac_burst_write.97462938542900957483304646364504405915689601740068529664956255299029309356476
    Line 1310, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 9.kmac_entropy_refresh.96679958222878318787432109796875879918342212154067210091195969961618040322550
    Line 828, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_app has 2 failures.
  - 29.kmac_app.17751042918240965330640668942200503480429833891690743931886065023321650801631
    Line 920, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.kmac_app.3408980270085476285376068786665798598924657826261514836285822669118748716451
    Line 983, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app has 3 failures.

10.kmac_app.8312329573005096661462013207338766786035952553412596862338968852610337938147
Line 519, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_app/latest/run.log

  UVM_FATAL @ 4234739131 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (100 [0x64] vs 195 [0xc3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4234739131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.kmac_app.50114898624681293251728719318936316120401500214550414299483244114895191106530
Line 599, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_app/latest/run.log

  UVM_FATAL @ 2373717024 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (187 [0xbb] vs 149 [0x95]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2373717024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 3.kmac_stress_all_with_rand_reset.46550583414661642586416763859807624609725392806243862940846548805655361527710
    Line 936, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15131972294 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 15131972294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.kmac_stress_all_with_rand_reset.14744137680252039748413869731815435090521404110355344176891447570901219434755
    Line 949, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19212198797 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 19212198797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test kmac_long_msg_and_output has 2 failures.
  - 27.kmac_long_msg_and_output.114780412710836206159609008359483017172769905318863870056051594089231721545447
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:a339914b-a089-498f-87d7-df500ae15165
```
  - 46.kmac_long_msg_and_output.94768548400022643113306270828301021234766092788400092144367534799701145056767
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:48d590e8-9f5c-41dd-8f9e-9e9b33a1a6ba
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 31.kmac_test_vectors_shake_128.13196368902087397480653004918109003687749776414539514729758455248880197530132
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  29943039 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  29943039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac_xof has 1 failures.
  - 47.kmac_test_vectors_kmac_xof.16482677087396266081592797468960482077783078972997249497481827442945036645896
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @  99386709 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  99386709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```