KMAC/MASKED Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.627m	8.019ms	48	50	96.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.250s	93.910us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	34.017us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.010s	8.759ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.770s	2.167ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.740s	419.090us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	34.017us	20	20	100.00
		kmac_csr_aliasing	10.770s	2.167ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.840s	14.485us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.560s	170.821us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	long_msg_and_output	kmac_long_msg_and_output	59.142m	223.918ms	50	50	100.00
V2	burst_write	kmac_burst_write	30.261m	30.119ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	48.486m	1.922s	50	50	100.00
		kmac_test_vectors_sha3_256	45.624m	1.555s	50	50	100.00
		kmac_test_vectors_sha3_384	32.078m	602.385ms	49	50	98.00
		kmac_test_vectors_sha3_512	24.007m	185.552ms	49	50	98.00
		kmac_test_vectors_shake_128	1.776h	1.038s	50	50	100.00
		kmac_test_vectors_shake_256	1.531h	2.151s	49	50	98.00
		kmac_test_vectors_kmac	7.970s	2.998ms	50	50	100.00
		kmac_test_vectors_kmac_xof	8.500s	1.061ms	50	50	100.00
V2	sideload	kmac_sideload	8.615m	124.260ms	50	50	100.00
V2	app	kmac_app	7.029m	14.533ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.470m	6.658ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.902m	56.507ms	49	50	98.00
V2	error	kmac_error	8.415m	72.792ms	48	50	96.00
V2	key_error	kmac_key_error	14.880s	6.494ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	56.520s	10.551ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.200s	1.642ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.178m	7.517ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.048m	968.258us	50	50	100.00
V2	stress_all	kmac_stress_all	50.462m	135.343ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.880s	14.302us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	17.792us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.700s	525.103us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.700s	525.103us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.250s	93.910us	5	5	100.00
		kmac_csr_rw	1.230s	34.017us	20	20	100.00
		kmac_csr_aliasing	10.770s	2.167ms	5	5	100.00
		kmac_same_csr_outstanding	3.180s	373.389us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.250s	93.910us	5	5	100.00
		kmac_csr_rw	1.230s	34.017us	20	20	100.00
		kmac_csr_aliasing	10.770s	2.167ms	5	5	100.00
		kmac_same_csr_outstanding	3.180s	373.389us	20	20	100.00
V2		TOTAL			1035	1050	98.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.430s	282.367us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.430s	282.367us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.430s	282.367us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.430s	282.367us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.460s	467.503us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	2.143m	32.912ms	5	5	100.00
		kmac_tl_intg_err	5.000s	282.955us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.000s	282.955us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.048m	968.258us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.627m	8.019ms	48	50	96.00
V2S	sec_cm_key_sideload	kmac_sideload	8.615m	124.260ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.430s	282.367us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.143m	32.912ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.143m	32.912ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.143m	32.912ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.627m	8.019ms	48	50	96.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.048m	968.258us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.143m	32.912ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.250m	59.496ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.627m	8.019ms	48	50	96.00
V2S		TOTAL			73	75	97.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	40.236m	45.239ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1221	1250	97.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	16	64.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.71	97.80	91.00	99.89	75.35	95.17	98.89	97.88

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:

Test kmac_test_vectors_shake_256 has 1 failures.

14.kmac_test_vectors_shake_256.65132618344026943521774146858297323622511528702114634034774353259916084516090
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @ 107696989 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 107696989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_smoke has 2 failures.

16.kmac_smoke.12456943045529449153720708007776827893457026509778502052459654338510095638931
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_smoke/latest/run.log

  UVM_ERROR @  38820178 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  38820178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.kmac_smoke.3855070136483252988240203778032620150892791599691388958561141048886304444054
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_smoke/latest/run.log

  UVM_ERROR @  28492191 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  28492191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_384 has 1 failures.

23.kmac_test_vectors_sha3_384.2968700209981656198409459826764061480144137932399273835925901040693172175083
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @ 118941761 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 118941761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_512 has 1 failures.

27.kmac_test_vectors_sha3_512.7188675716919559759608111970483627964547646862908082040406074611965579597118
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  30851481 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  30851481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

38.kmac_stress_all.10114906490547069254950279183025932800417759556750908347654838727175130158702
Line 1291, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_stress_all/latest/run.log

  UVM_ERROR @ 58939093291 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 58939093291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.111989605476727791172798873638284988552289426636529552593220351042369261536011
    Line 1739, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 79922419272 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 79922419272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.12922774771432527363191603697503122926670394546444123993582836993956344105569
    Line 4340, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45238833335 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 45238833335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.4212301039825129867933352567337311191221258348373880841773299004391513230680
    Line 338, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3126042839 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3126042839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.97999946059220759035525190111676876359599638034696312735782353117145986461881
    Line 2339, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 73906478114 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 73906478114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 3 failures.
  - 0.kmac_burst_write.48829265885546696565599480602420102913092501622007233653600182963328579440233
    Line 1064, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.kmac_burst_write.74375373976124321190181105816354969472640311254432129795035787469432743393842
    Line 944, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_error has 1 failures.
  - 8.kmac_error.74895807961164476330774009813991049655890908026840636835777248106202040773451
    Line 1123, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_mubi has 1 failures.

3.kmac_mubi.24732579662799690922111917927235650274086806417297655389991500901378151175130
Line 603, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_mubi/latest/run.log

  UVM_FATAL @ 26583636002 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (208 [0xd0] vs 156 [0x9c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 26583636002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

8.kmac_stress_all.37950799165341718421780845267418753405485535632579046342843744444816375966329
Line 1175, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all/latest/run.log

  UVM_FATAL @ 18012227355 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (72 [0x48] vs 227 [0xe3]) Mismatch between unmasked_digest[1] and dpi_digest[1]
  UVM_INFO @ 18012227355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

45.kmac_entropy_refresh.32082876075935708517017616295505219918749749290914658853839191604772023555249
Line 667, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 56480266506 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (210 [0xd2] vs 44 [0x2c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 56480266506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

48.kmac_app.3929949049924123169463073274018660410575062014446912045370095177655569817208
Line 567, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_app/latest/run.log

  UVM_FATAL @ 5084403083 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (16 [0x10] vs 76 [0x4c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5084403083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_error has 1 failures.
  - 0.kmac_error.30194499859342594525320638083843391417726807485754311082915816263299010011615
    Line 353, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_error/latest/run.log
```
  UVM_FATAL @ 10586256901 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10586256901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 2 failures.
  - 7.kmac_stress_all.89185176844768624301417517564970663014594025103044992399692028465326031374091
    Line 454, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 28686407905 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 28686407905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.kmac_stress_all.4058075895737582947857841190663315882129273427767126085942428169508037655900
    Line 1386, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 88197011337 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 88197011337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 2.kmac_key_error.9042277176590627038648370283016851792219170682564146789351120306415421655494
    Line 275, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 1201425598 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 1201425598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 18.kmac_shadow_reg_errors_with_csr_rw.34734220988033202930135801873858913848811144165114502789252362406109670947888
    Line 256, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @ 105084544 ps: (kmac_csr_assert_fpv.sv:367) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @ 105084544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```