KMAC/MASKED Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.572m	4.527ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	97.883us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.370s	100.793us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.490s	3.560ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.820s	522.066us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.540s	76.637us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.370s	100.793us	20	20	100.00
		kmac_csr_aliasing	9.820s	522.066us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.830s	14.577us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	153.390us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.036m	657.262ms	41	50	82.00
V2	burst_write	kmac_burst_write	30.607m	15.820ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	58.962m	355.974ms	40	50	80.00
		kmac_test_vectors_sha3_256	58.895m	185.651ms	49	50	98.00
		kmac_test_vectors_sha3_384	52.694m	1.423s	50	50	100.00
		kmac_test_vectors_sha3_512	32.007m	201.352ms	50	50	100.00
		kmac_test_vectors_shake_128	1.970h	225.963ms	21	50	42.00
		kmac_test_vectors_shake_256	1.636h	55.932ms	17	50	34.00
		kmac_test_vectors_kmac	7.690s	1.008ms	50	50	100.00
		kmac_test_vectors_kmac_xof	8.530s	977.846us	50	50	100.00
V2	sideload	kmac_sideload	10.705m	21.961ms	50	50	100.00
V2	app	kmac_app	6.759m	70.384ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.908m	12.236ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.820m	21.811ms	49	50	98.00
V2	error	kmac_error	9.218m	84.138ms	50	50	100.00
V2	key_error	kmac_key_error	14.480s	1.845ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	54.290s	5.765ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.880s	3.236ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.103m	6.071ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	38.660s	4.703ms	50	50	100.00
V2	stress_all	kmac_stress_all	55.975m	85.417ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.890s	46.585us	50	50	100.00
V2	alert_test	kmac_alert_test	0.950s	143.628us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.450s	197.227us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.450s	197.227us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	97.883us	5	5	100.00
		kmac_csr_rw	1.370s	100.793us	20	20	100.00
		kmac_csr_aliasing	9.820s	522.066us	5	5	100.00
		kmac_same_csr_outstanding	2.790s	245.193us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	97.883us	5	5	100.00
		kmac_csr_rw	1.370s	100.793us	20	20	100.00
		kmac_csr_aliasing	9.820s	522.066us	5	5	100.00
		kmac_same_csr_outstanding	2.790s	245.193us	20	20	100.00
V2		TOTAL			962	1050	91.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.470s	55.826us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.470s	55.826us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.470s	55.826us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.470s	55.826us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.490s	164.319us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.771m	16.596ms	5	5	100.00
		kmac_tl_intg_err	5.110s	249.859us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.110s	249.859us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	38.660s	4.703ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.572m	4.527ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.705m	21.961ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.470s	55.826us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.771m	16.596ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.771m	16.596ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.771m	16.596ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.572m	4.527ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	38.660s	4.703ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.771m	16.596ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.672m	84.462ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.572m	4.527ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	46.338m	413.055ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			1156	1250	92.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.58	99.89	76.76	95.53	98.89	97.88

Failure Buckets

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 82 failures:
- Test kmac_test_vectors_sha3_224 has 10 failures.
  - 1.kmac_test_vectors_sha3_224.66577641370446916763603286716405412024815966104415226411675295513132560610103
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:776389af-a773-4e98-a2ee-9acfd043a3d4
```
  - 7.kmac_test_vectors_sha3_224.8363011040150501836007287033049156785329732859847947407577259381051110945639
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:da734ea3-0ad5-4731-98d8-914fc36ce057
```
  - ... and 8 more failures.
- Test kmac_test_vectors_shake_128 has 29 failures.
  - 1.kmac_test_vectors_shake_128.12892756889093611914840768004582436033430183484143692635606511362721363490536
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:0018ef97-9dfd-4d8a-b2e5-244ee3f71a2b
```
  - 2.kmac_test_vectors_shake_128.25514268152486317778407702197966683037633807282906751688145702503504584083476
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:067ad603-6380-46bd-ae33-98e05b75cb83
```
  - ... and 27 more failures.
- Test kmac_test_vectors_shake_256 has 33 failures.
  - 2.kmac_test_vectors_shake_256.35760774420431362406140195564934174330184438314715819688577203730070169891357
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:81965483-b4a0-4619-b31a-fc0a88a60123
```
  - 3.kmac_test_vectors_shake_256.22998720980384565480034258238072694946960730372525650179812874957774942987508
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:ccd7e89e-8e8f-48a0-b789-0de152b8fe8f
```
  - ... and 31 more failures.
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 7.kmac_test_vectors_sha3_256.69083966675791598030564967481665094971322930315808748435515740556820711008351
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_sha3_256/latest/run.log
```
  Job ID: smart:db5cbb63-1e7f-4032-8adc-33eb1bc7ccf6
```
- Test kmac_long_msg_and_output has 9 failures.
  - 8.kmac_long_msg_and_output.43466821772267538451748922646731396923630192812932830754380077264612561121415
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:c4354768-3ad2-4723-a3c4-ebfca20969a1
```
  - 10.kmac_long_msg_and_output.51457011702399750153245412090337050373417899777763480127161781999977405736691
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:b3a8e35a-2566-45fb-a40a-f383170208a5
```
  - ... and 7 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 6 failures:

Test kmac_entropy_refresh has 1 failures.

2.kmac_entropy_refresh.102587013614668564553787988415934550540664555920237256910602045962880659854691
Line 637, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 6526221790 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (206 [0xce] vs 244 [0xf4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6526221790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

2.kmac_stress_all.9839903615801200809842246219096543234869971772361812277800247467304432746242
Line 1571, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all/latest/run.log

  UVM_FATAL @ 16399058217 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (86 [0x56] vs 73 [0x49]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16399058217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.kmac_stress_all.102564477390877729472279555045640294251128764346538742680776016792655591503414
Line 1243, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all/latest/run.log

  UVM_FATAL @ 60898919363 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (125 [0x7d] vs 38 [0x26]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 60898919363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 3 failures.

10.kmac_app.77647588483905967322622479200688407787980831083359501171488836539303520741493
Line 321, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_app/latest/run.log

  UVM_FATAL @ 1476411178 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (7 [0x7] vs 81 [0x51]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1476411178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.kmac_app.44901213726281260639760139910769794399485540592257252395638943967099768399611
Line 275, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_app/latest/run.log

  UVM_FATAL @ 299839927 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (176 [0xb0] vs 235 [0xeb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 299839927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 0.kmac_stress_all_with_rand_reset.44895982899677988807687959069988312602321536194281424353575879243059154272977
    Line 346, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8269048955 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 8269048955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.42052417793199453776680302022073074394537831928207979301437894402111525449391
    Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 126497647 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 126497647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 5.kmac_stress_all_with_rand_reset.112447274393772689732807848718338478098099187362180088908603178669858837907149
    Line 562, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10034580701 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10034580701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.55705635169934873239205982714405608523614151727395802520214972085532089532388
    Line 730, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57704157856 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 57704157856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 14.kmac_shadow_reg_errors_with_csr_rw.47616008420483371344293094809635515232380439727404762205840481148551268386361
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  31362990 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (159 [0x9f] vs 0 [0x0]) Regname: kmac_reg_block.entropy_period reset value: 0x0
  UVM_INFO @  31362990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```