KMAC/MASKED Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.549m	3.473ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	124.102us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.350s	30.042us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.410s	1.589ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.290s	1.040ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.620s	91.253us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.350s	30.042us	20	20	100.00
		kmac_csr_aliasing	10.290s	1.040ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.820s	16.512us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.290s	32.273us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.122m	72.963ms	35	50	70.00
V2	burst_write	kmac_burst_write	29.491m	123.182ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	59.210m	67.540ms	42	50	84.00
		kmac_test_vectors_sha3_256	58.965m	674.782ms	48	50	96.00
		kmac_test_vectors_sha3_384	47.530m	877.956ms	50	50	100.00
		kmac_test_vectors_sha3_512	35.252m	998.656ms	50	50	100.00
		kmac_test_vectors_shake_128	1.905h	135.776ms	22	50	44.00
		kmac_test_vectors_shake_256	1.652h	58.004ms	21	50	42.00
		kmac_test_vectors_kmac	7.740s	296.811us	49	50	98.00
		kmac_test_vectors_kmac_xof	7.640s	1.051ms	50	50	100.00
V2	sideload	kmac_sideload	9.706m	54.107ms	50	50	100.00
V2	app	kmac_app	7.443m	276.300ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.626m	88.629ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	8.760m	145.491ms	48	50	96.00
V2	error	kmac_error	9.764m	63.273ms	50	50	100.00
V2	key_error	kmac_key_error	14.830s	9.445ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	48.580s	2.222ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.850s	1.125ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.205m	7.516ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	48.350s	805.277us	50	50	100.00
V2	stress_all	kmac_stress_all	1.058h	1.803s	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	15.980us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	18.833us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.100s	172.801us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.100s	172.801us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	124.102us	5	5	100.00
		kmac_csr_rw	1.350s	30.042us	20	20	100.00
		kmac_csr_aliasing	10.290s	1.040ms	5	5	100.00
		kmac_same_csr_outstanding	2.390s	176.713us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	124.102us	5	5	100.00
		kmac_csr_rw	1.350s	30.042us	20	20	100.00
		kmac_csr_aliasing	10.290s	1.040ms	5	5	100.00
		kmac_same_csr_outstanding	2.390s	176.713us	20	20	100.00
V2		TOTAL			962	1050	91.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.550s	341.183us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.550s	341.183us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.550s	341.183us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.550s	341.183us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.240s	133.322us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.039m	9.554ms	5	5	100.00
		kmac_tl_intg_err	5.090s	266.884us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.090s	266.884us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	48.350s	805.277us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.549m	3.473ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.706m	54.107ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.550s	341.183us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.039m	9.554ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.039m	9.554ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.039m	9.554ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.549m	3.473ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	48.350s	805.277us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.039m	9.554ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.176m	12.884ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.549m	3.473ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	24.222m	195.684ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1153	1250	92.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	15	60.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.22	97.91	92.62	99.89	76.76	95.59	99.05	97.73

Failure Buckets

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 81 failures:
- Test kmac_test_vectors_shake_128 has 27 failures.
  - 0.kmac_test_vectors_shake_128.11025088414661302387259625850754552315971192149546710050530591896985944121480
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:e79791a0-76c7-4ac8-af6f-f3692b242e3d
```
  - 2.kmac_test_vectors_shake_128.28814667549115946240125705110215597314123904281174753551407587308669403119203
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:f3364dfb-79b3-4367-bf84-b23fcc672bfc
```
  - ... and 25 more failures.
- Test kmac_test_vectors_shake_256 has 29 failures.
  - 1.kmac_test_vectors_shake_256.98011336777105897335502515955057000629491133172575794102790615257411913950951
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:bc18f03f-0ef2-470c-b937-f3c4267cdf12
```
  - 2.kmac_test_vectors_shake_256.1398170726009704632039106165212728918419270519845124275249331073144910478572
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:b456dba9-9507-4b8c-b849-27a0aacde6e2
```
  - ... and 27 more failures.
- Test kmac_long_msg_and_output has 15 failures.
  - 3.kmac_long_msg_and_output.28467082418373317006029449444088895634342741390090110235794820583885847118880
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:b21c3717-0d84-4e67-87ec-71621930d1d7
```
  - 4.kmac_long_msg_and_output.65334744180009217481680637433769693669266632006369491083609583494047637253767
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:74c7594b-bed8-451b-b36a-aae05082bf19
```
  - ... and 13 more failures.
- Test kmac_test_vectors_sha3_256 has 2 failures.
  - 5.kmac_test_vectors_sha3_256.83276261726108630191392564423593552015756823752552452788109182581192320259584
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_sha3_256/latest/run.log
```
  Job ID: smart:52a8f260-9754-473a-8250-5183cff06f4c
```
  - 48.kmac_test_vectors_sha3_256.16352190645739073622577651621912265882275298856795012905593983650187665996968
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_test_vectors_sha3_256/latest/run.log
```
  Job ID: smart:0ae2e354-85ad-4d74-bcf7-c74ad041c2fc
```
- Test kmac_test_vectors_sha3_224 has 8 failures.
  - 6.kmac_test_vectors_sha3_224.88546194466033835154787918734055821788302294110281508317719910457846201852543
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:19d2bf9c-c5fd-451a-8d4c-98d78992816a
```
  - 8.kmac_test_vectors_sha3_224.113521807518803834980411954016664565458252853796024603405491842324144549661069
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:33803fa1-18b5-4c31-9645-093bde5ec87d
```
  - ... and 6 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.106944619232463141484347662588000505796273350636452087538889413713747074829421
    Line 322, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6808529554 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6808529554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.10854961194244816979177101600722895421254711774752080855851625947191988589874
    Line 726, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16700203781 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16700203781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 1 failures.

6.kmac_app.94530568849526598306585243541293651796809861353932260633653681097755567601372
Line 671, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_app/latest/run.log

  UVM_FATAL @ 2558350049 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (214 [0xd6] vs 240 [0xf0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2558350049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app_with_partial_data has 1 failures.

8.kmac_app_with_partial_data.50509388554026149655495832429692802582042673071513574847763530058836088149075
Line 413, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 4381221685 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (127 [0x7f] vs 24 [0x18]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4381221685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

8.kmac_entropy_refresh.27986890330308824597807919044796594070005161279891693109227962346157144003534
Line 447, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3793673511 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (188 [0xbc] vs 198 [0xc6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3793673511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.kmac_entropy_refresh.17586400372879662808201432105474084410014562750544670862454331487735628176998
Line 543, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2432918726 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (204 [0xcc] vs 66 [0x42]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2432918726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_stress_all has 1 failures.
  - 3.kmac_stress_all.107895572150225776338315685247867410195126210782381735502992168290270209011483
    Line 1254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 22487288377 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 22487288377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 29.kmac_test_vectors_shake_128.87631524342224160831953936259259486555116228967136600448965293483368487410587
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  22853441 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  22853441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac has 1 failures.
  - 38.kmac_test_vectors_kmac.10801794113470809103108093879148219475734000200520354369583300583930875811282
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  35988289 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  35988289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 1.kmac_stress_all_with_rand_reset.73457435440850214014327111216576913274845660023225673670829299653693249990194
    Line 1220, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9994502832 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9994502832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.73614161578054916857818245994931936810316692130605794249647547621263188611815
    Line 306, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 762536308 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 762536308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```