KMAC/MASKED Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.607m	17.663ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	56.952us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.300s	407.050us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.310s	1.012ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.650s	523.290us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.860s	352.214us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.300s	407.050us	20	20	100.00
		kmac_csr_aliasing	9.650s	523.290us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	26.930us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.530s	133.327us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.457h	308.265ms	45	50	90.00
V2	burst_write	kmac_burst_write	30.013m	15.810ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.162h	1.938s	50	50	100.00
		kmac_test_vectors_sha3_256	1.062h	1.117s	50	50	100.00
		kmac_test_vectors_sha3_384	47.112m	291.258ms	50	50	100.00
		kmac_test_vectors_sha3_512	31.860m	438.310ms	50	50	100.00
		kmac_test_vectors_shake_128	2.095h	1.216s	21	50	42.00
		kmac_test_vectors_shake_256	2.961h	235.113ms	47	50	94.00
		kmac_test_vectors_kmac	7.400s	1.111ms	50	50	100.00
		kmac_test_vectors_kmac_xof	10.530s	1.388ms	50	50	100.00
V2	sideload	kmac_sideload	11.517m	23.257ms	50	50	100.00
V2	app	kmac_app	6.969m	73.337ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.605m	12.754ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.588m	77.929ms	49	50	98.00
V2	error	kmac_error	8.660m	154.699ms	50	50	100.00
V2	key_error	kmac_key_error	14.170s	17.687ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.420s	1.209ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	30.140s	6.248ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.160m	22.963ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	47.530s	898.968us	50	50	100.00
V2	stress_all	kmac_stress_all	1.141h	434.791ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.860s	22.219us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	19.053us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.160s	330.879us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.160s	330.879us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	56.952us	5	5	100.00
		kmac_csr_rw	1.300s	407.050us	20	20	100.00
		kmac_csr_aliasing	9.650s	523.290us	5	5	100.00
		kmac_same_csr_outstanding	2.940s	475.219us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	56.952us	5	5	100.00
		kmac_csr_rw	1.300s	407.050us	20	20	100.00
		kmac_csr_aliasing	9.650s	523.290us	5	5	100.00
		kmac_same_csr_outstanding	2.940s	475.219us	20	20	100.00
V2		TOTAL			1011	1050	96.29
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.500s	53.949us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.500s	53.949us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.500s	53.949us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.500s	53.949us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.150s	1.146ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.058m	37.431ms	5	5	100.00
		kmac_tl_intg_err	5.450s	955.637us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.450s	955.637us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	47.530s	898.968us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.607m	17.663ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	11.517m	23.257ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.500s	53.949us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.058m	37.431ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.058m	37.431ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.058m	37.431ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.607m	17.663ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	47.530s	898.968us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.058m	37.431ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.056m	15.363ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.607m	17.663ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	20.432m	120.943ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1202	1250	96.16

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.23	97.91	92.65	99.89	76.76	95.59	99.05	97.73

Failure Buckets

• Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 37 failures:

  • Test kmac_test_vectors_shake_128 has 29 failures.

    • 0.kmac_test_vectors_shake_128.96739087564404984530776758498619089475565944985992853248920210301822485776819
      Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log

        Job ID: smart:4e627727-d282-4e9d-ae08-f4788c2b4ab5
      

    • 1.kmac_test_vectors_shake_128.61832619178219492646556949989898929587242771872116543695994312969797556149208
      Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log

        Job ID: smart:33f9289f-aff9-4652-a130-681df98ff66b
      

    • ... and 27 more failures.

  • Test kmac_long_msg_and_output has 5 failures.

    • 16.kmac_long_msg_and_output.32451825522795449570279140197342489354684063207376541051024475068464707957327
      Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest/run.log

        Job ID: smart:95159464-c9f8-4c87-b9a4-1cfe49747c8b
      

    • 21.kmac_long_msg_and_output.107717768246747448977945540708258128240785721712532487104298737938151147087205
      Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest/run.log

        Job ID: smart:1e8cddf7-65e5-4d7d-b8f5-327dc8457698
      

    • ... and 3 more failures.

  • Test kmac_test_vectors_shake_256 has 3 failures.

    • 19.kmac_test_vectors_shake_256.47881953264562748006857332584410526175312690283852481372364927158934247720271
      Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_shake_256/latest/run.log

        Job ID: smart:61aaaa15-de00-4ccb-b83c-b707ec674062
      

    • 37.kmac_test_vectors_shake_256.8631701318007696924189441907078813136538248815447645782155726266890381020429
      Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_shake_256/latest/run.log

        Job ID: smart:3a239375-8181-4267-aad7-48020bee9f1d
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:

  • Test kmac_stress_all_with_rand_reset has 7 failures.

    • 0.kmac_stress_all_with_rand_reset.22181750924344303818205663174266263669924012436713070776985900015779087769007
      Line 332, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4487286896 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4487286896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.kmac_stress_all_with_rand_reset.115737473420905035930191837978433655155227882366418807352372516418618892779173
      Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 213109938 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 213109938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

  • Test kmac_entropy_refresh has 1 failures.

    • 11.kmac_entropy_refresh.92367643058489331361484617282559617866108640891551646670940250488915904962273
      Line 285, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 609017857 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (172 [0xac] vs 175 [0xaf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 609017857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_app has 1 failures.

    • 45.kmac_app.38092228913855692745718761045977285597782053987231283142640364494941223632817
      Line 357, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_app/latest/run.log

        UVM_FATAL @ 814978201 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (255 [0xff] vs 119 [0x77]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 814978201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 9.kmac_stress_all_with_rand_reset.38335971496796750671150098655178237846224413856827377287481633326143314047406
      Line 1343, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 61287742632 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 61287742632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_smoke has 1 failures.

    • 38.kmac_smoke.35707420108903887435086586317718461560062483375315375770979507615640565149740
      Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_smoke/latest/run.log

        UVM_ERROR @  92839476 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  92839476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.08_09.00.27
• 2024.08.07_08.53.17
• 2024.08.06_09.25.46
• 2024.08.05_10.53.31
• 2024.08.04_06.41.47
• 2024.08.03_08.52.40
• 2024.08.02_08.07.45