KMAC/MASKED Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.629m	27.636ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	31.790us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	48.556us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.010s	1.171ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.470s	1.523ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.110s	1.326ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	48.556us	20	20	100.00
		kmac_csr_aliasing	9.470s	1.523ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	84.987us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.630s	132.286us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.466h	98.071ms	46	50	92.00
V2	burst_write	kmac_burst_write	29.271m	148.141ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.177h	1.377s	50	50	100.00
		kmac_test_vectors_sha3_256	1.065h	189.088ms	50	50	100.00
		kmac_test_vectors_sha3_384	48.279m	282.444ms	50	50	100.00
		kmac_test_vectors_sha3_512	32.718m	194.797ms	50	50	100.00
		kmac_test_vectors_shake_128	1.909h	549.211ms	23	50	46.00
		kmac_test_vectors_shake_256	2.984h	1.281s	41	50	82.00
		kmac_test_vectors_kmac	7.630s	736.485us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.360s	1.830ms	50	50	100.00
V2	sideload	kmac_sideload	9.844m	62.639ms	50	50	100.00
V2	app	kmac_app	7.489m	232.442ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.411m	63.825ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.202m	36.407ms	48	50	96.00
V2	error	kmac_error	9.369m	81.752ms	50	50	100.00
V2	key_error	kmac_key_error	14.210s	3.935ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.150s	1.175ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	28.970s	1.984ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.536m	35.903ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	51.640s	800.828us	50	50	100.00
V2	stress_all	kmac_stress_all	50.033m	359.675ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.910s	17.923us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	47.788us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.800s	150.734us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.800s	150.734us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	31.790us	5	5	100.00
		kmac_csr_rw	1.260s	48.556us	20	20	100.00
		kmac_csr_aliasing	9.470s	1.523ms	5	5	100.00
		kmac_same_csr_outstanding	2.930s	126.471us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	31.790us	5	5	100.00
		kmac_csr_rw	1.260s	48.556us	20	20	100.00
		kmac_csr_aliasing	9.470s	1.523ms	5	5	100.00
		kmac_same_csr_outstanding	2.930s	126.471us	20	20	100.00
V2		TOTAL			1008	1050	96.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.580s	62.770us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.580s	62.770us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.580s	62.770us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.580s	62.770us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.240s	139.238us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.859m	28.488ms	5	5	100.00
		kmac_tl_intg_err	6.710s	4.658ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.710s	4.658ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	51.640s	800.828us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.629m	27.636ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.844m	62.639ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.580s	62.770us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.859m	28.488ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.859m	28.488ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.859m	28.488ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.629m	27.636ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	51.640s	800.828us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.859m	28.488ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.047m	25.008ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.629m	27.636ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.043h	337.569ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1202	1250	96.16

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.15	97.91	92.65	99.89	76.06	95.59	99.05	97.88

Failure Buckets

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 40 failures:
- Test kmac_test_vectors_shake_128 has 27 failures.
  - 1.kmac_test_vectors_shake_128.13426097885355136083959728639112624700074376965897828498616308922109218855700
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:9562e30e-569c-413e-b13c-6a375f775364
```
  - 2.kmac_test_vectors_shake_128.91368315959495419593772878149077979039649683098770801535107500776274642416962
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:27814bc7-5f38-41fa-90b8-b74009c94e8f
```
  - ... and 25 more failures.
- Test kmac_test_vectors_shake_256 has 9 failures.
  - 3.kmac_test_vectors_shake_256.103407692365797883637654892001805752900702297788396779386200506743776827697219
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:44036d5d-b51d-4b4b-bdea-11d917754078
```
  - 10.kmac_test_vectors_shake_256.70969763362390322764889469327235352955914115035413750446013241536898745995007
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:ac1b5c65-f48a-4d33-95fc-3b6300179a2e
```
  - ... and 7 more failures.
- Test kmac_long_msg_and_output has 4 failures.
  - 9.kmac_long_msg_and_output.8641736027914453430887848517310445721152751206875702131073359641709163999268
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:90b94343-a7d3-44ca-9687-ea26d2ab503a
```
  - 33.kmac_long_msg_and_output.23755025497938971339973675040788488219365016064209258796216981797090813210571
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:16d468d2-ce83-4b25-912c-19cfa67193ae
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.102479212152565844475592143057390554754369887108501870177293911733371535085124
    Line 349, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20876379264 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20876379264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.83245363538852713727184147094947993985948280553136296923700312169478272127345
    Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 949834019 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 949834019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_entropy_refresh has 2 failures.

11.kmac_entropy_refresh.55233551304344460249912401380766168110877753718775517182079315472941022561563
Line 947, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 50849013195 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (214 [0xd6] vs 45 [0x2d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 50849013195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.kmac_entropy_refresh.32694761566356501192793441664874003280863630385556629894417235313661303268733
Line 439, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2464019182 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (218 [0xda] vs 96 [0x60]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2464019182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 6.kmac_stress_all_with_rand_reset.40662966464310219627279170803590268299627003978857226954476524831685119009337
    Line 452, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12945526923 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 12945526923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```