KMAC/MASKED Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.589m	5.238ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	54.124us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	71.147us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.490s	1.101ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.480s	7.498ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.610s	36.373us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	71.147us	20	20	100.00
		kmac_csr_aliasing	9.480s	7.498ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	11.654us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	74.719us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.472h	78.648ms	49	50	98.00
V2	burst_write	kmac_burst_write	30.221m	152.980ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.145h	1.606s	50	50	100.00
		kmac_test_vectors_sha3_256	1.018h	91.092ms	50	50	100.00
		kmac_test_vectors_sha3_384	47.598m	297.707ms	50	50	100.00
		kmac_test_vectors_sha3_512	31.886m	170.981ms	50	50	100.00
		kmac_test_vectors_shake_128	2.992h	189.796ms	29	50	58.00
		kmac_test_vectors_shake_256	2.872h	1.001s	45	50	90.00
		kmac_test_vectors_kmac	7.600s	274.876us	50	50	100.00
		kmac_test_vectors_kmac_xof	9.000s	678.951us	50	50	100.00
V2	sideload	kmac_sideload	10.029m	23.385ms	50	50	100.00
V2	app	kmac_app	7.702m	35.044ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.933m	60.283ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.564m	87.583ms	48	50	96.00
V2	error	kmac_error	9.248m	24.697ms	50	50	100.00
V2	key_error	kmac_key_error	13.790s	17.007ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	48.230s	7.013ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	49.650s	681.130us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	49.020s	5.257ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	48.680s	713.849us	50	50	100.00
V2	stress_all	kmac_stress_all	1.008h	246.471ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.930s	49.875us	50	50	100.00
V2	alert_test	kmac_alert_test	0.950s	188.944us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.240s	805.366us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.240s	805.366us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	54.124us	5	5	100.00
		kmac_csr_rw	1.210s	71.147us	20	20	100.00
		kmac_csr_aliasing	9.480s	7.498ms	5	5	100.00
		kmac_same_csr_outstanding	3.410s	2.124ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	54.124us	5	5	100.00
		kmac_csr_rw	1.210s	71.147us	20	20	100.00
		kmac_csr_aliasing	9.480s	7.498ms	5	5	100.00
		kmac_same_csr_outstanding	3.410s	2.124ms	20	20	100.00
V2		TOTAL			1017	1050	96.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.320s	53.672us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.320s	53.672us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.320s	53.672us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.320s	53.672us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.230s	1.860ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.039m	9.195ms	5	5	100.00
		kmac_tl_intg_err	5.380s	1.977ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.380s	1.977ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	48.680s	713.849us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.589m	5.238ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	10.029m	23.385ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.320s	53.672us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.039m	9.195ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.039m	9.195ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.039m	9.195ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.589m	5.238ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	48.680s	713.849us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.039m	9.195ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.048m	55.085ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.589m	5.238ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	29.664m	559.378ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1208	1250	96.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.51	97.89	92.65	99.89	78.87	95.53	98.89	97.88

Failure Buckets

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test kmac_test_vectors_shake_128 has 21 failures.
  - 3.kmac_test_vectors_shake_128.1923537096725788534456530796409174409924898990283603758455029757106089297307
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:04b93b4c-b9f5-41db-aa08-d93e48625678
```
  - 4.kmac_test_vectors_shake_128.4883093986399282450418397578454879810954528074708735041064598623483660170600
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:4563a9be-4f0e-4577-91a3-70536ccff205
```
  - ... and 19 more failures.
- Test kmac_test_vectors_shake_256 has 2 failures.
  - 35.kmac_test_vectors_shake_256.13054101076355499023792757272520878012411462920056673121176380561748964404953
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:2da05dec-3cdc-4f8c-9a39-6a11bbb79cd7
```
  - 45.kmac_test_vectors_shake_256.64702526798119008851700978409024741633993977405915766679291508649255435231115
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:e73bbcd4-8642-4397-98a7-cb02b9fdc598
```
- Test kmac_long_msg_and_output has 1 failures.
  - 36.kmac_long_msg_and_output.18660477300842183651885106364843918695491664697661913979114003198382175652765
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:e457545f-17fb-453f-8b34-d29edae2f843
```
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.92692720509848143310443000878232350373521178123272235983334434659547609194945
    Line 1593, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 559377783599 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 559377783599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.52603340518893816230844850839046335406180849914076577356103027671387912291040
    Line 1854, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41616212286 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 41616212286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 7 failures:

Test kmac_test_vectors_shake_256 has 3 failures.

3.kmac_test_vectors_shake_256.57050387970504242037719892553186872189554621651166723120781650398564854415801
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  31202301 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  31202301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_test_vectors_shake_256.53687632174890675064739851142696400006904761546135077870659420395973441366353
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  40978943 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  40978943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_burst_write has 1 failures.

16.kmac_burst_write.5386032877733626450073558405177552390616273339494613373350181086062832227702
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_burst_write/latest/run.log

  UVM_ERROR @  49728316 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  49728316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

18.kmac_stress_all.96688712950191155754603040840667945820173409131167966973985243720408083180825
Line 782, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all/latest/run.log

  UVM_ERROR @ 31585479750 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 31585479750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.kmac_stress_all.49344752670917195771840120301167080227720169647732031402855329854521666472927
Line 379, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_stress_all/latest/run.log

  UVM_ERROR @ 3152385563 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 3152385563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_smoke has 1 failures.

31.kmac_smoke.86825252073802795043190397218394258585377082286963255041965686133881134938574
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_smoke/latest/run.log

  UVM_ERROR @  83130249 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  83130249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_entropy_refresh has 2 failures.

16.kmac_entropy_refresh.29891117245895325710664773788419033292240439374463872318516644519091726669087
Line 397, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 6644418668 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (191 [0xbf] vs 199 [0xc7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6644418668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.kmac_entropy_refresh.172851711715267307330862060821763018392518841187564069401126122247245738407
Line 369, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 1592078416 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (248 [0xf8] vs 227 [0xe3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1592078416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 9.kmac_stress_all_with_rand_reset.99883305751898318360025172528190817553319379863535594930123443538430517698771
    Line 670, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 59335570310 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 59335570310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 44.kmac_key_error.69936284131753094072250309345590498949968954394727016574671398085158921394745
    Line 275, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 1026253713 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 1026253713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```