KMAC/MASKED Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.663m	7.956ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.240s	48.832us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.280s	214.589us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.920s	5.649ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.510s	1.699ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.730s	39.401us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.280s	214.589us	20	20	100.00
		kmac_csr_aliasing	9.510s	1.699ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	10.285us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	40.158us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.473h	82.278ms	46	50	92.00
V2	burst_write	kmac_burst_write	30.154m	199.161ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.181h	439.443ms	50	50	100.00
		kmac_test_vectors_sha3_256	1.227h	1.874s	49	50	98.00
		kmac_test_vectors_sha3_384	48.375m	283.176ms	49	50	98.00
		kmac_test_vectors_sha3_512	32.744m	48.363ms	49	50	98.00
		kmac_test_vectors_shake_128	1.873h	62.795ms	17	50	34.00
		kmac_test_vectors_shake_256	2.988h	447.182ms	44	50	88.00
		kmac_test_vectors_kmac	7.790s	580.705us	49	50	98.00
		kmac_test_vectors_kmac_xof	8.460s	1.985ms	50	50	100.00
V2	sideload	kmac_sideload	10.036m	61.556ms	50	50	100.00
V2	app	kmac_app	7.589m	17.649ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.006m	12.743ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.863m	98.609ms	49	50	98.00
V2	error	kmac_error	9.450m	18.185ms	49	50	98.00
V2	key_error	kmac_key_error	16.320s	7.082ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	59.440s	33.187ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.960s	2.816ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.462m	32.421ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	30.520s	1.681ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.222h	99.686ms	49	50	98.00
V2	intr_test	kmac_intr_test	1.010s	24.284us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	15.253us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.360s	1.772ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.360s	1.772ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.240s	48.832us	5	5	100.00
		kmac_csr_rw	1.280s	214.589us	20	20	100.00
		kmac_csr_aliasing	9.510s	1.699ms	5	5	100.00
		kmac_same_csr_outstanding	3.060s	122.647us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.240s	48.832us	5	5	100.00
		kmac_csr_rw	1.280s	214.589us	20	20	100.00
		kmac_csr_aliasing	9.510s	1.699ms	5	5	100.00
		kmac_same_csr_outstanding	3.060s	122.647us	20	20	100.00
V2		TOTAL			999	1050	95.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.540s	99.925us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.540s	99.925us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.540s	99.925us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.540s	99.925us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.310s	126.670us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.943m	17.251ms	5	5	100.00
		kmac_tl_intg_err	6.010s	365.627us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.010s	365.627us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	30.520s	1.681ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.663m	7.956ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.036m	61.556ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.540s	99.925us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.943m	17.251ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.943m	17.251ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.943m	17.251ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.663m	7.956ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	30.520s	1.681ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.943m	17.251ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.055m	96.513ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.663m	7.956ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	35.966m	279.649ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1193	1250	95.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	14	56.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.25	97.91	92.68	99.89	76.76	95.59	99.05	97.88

Failure Buckets

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 42 failures:
- Test kmac_long_msg_and_output has 4 failures.
  - 0.kmac_long_msg_and_output.55869189319578156175429336539996805701576311562439987187443617272194135609743
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:38df917c-2959-4975-94d1-ea1bfd108980
```
  - 8.kmac_long_msg_and_output.57527276515298981970351880615198152675453009957665450522002414980572465836635
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:8bd998c6-579d-48b0-9a2a-3628475b730b
```
  - ... and 2 more failures.
- Test kmac_test_vectors_shake_128 has 32 failures.
  - 0.kmac_test_vectors_shake_128.114835102521987585337422048939158626513244160939031662543424562852716548056059
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:5b7faa96-7ca8-4fc2-b231-4b91e4ee9670
```
  - 1.kmac_test_vectors_shake_128.84124458639341465013599045196340688570227272833937673380033659016141299032086
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:a2c38a3e-1722-4daf-8702-f89347a31f05
```
  - ... and 30 more failures.
- Test kmac_test_vectors_shake_256 has 6 failures.
  - 13.kmac_test_vectors_shake_256.31666226477940257654639692155773907547967981377243567971561050675878489047972
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:90b83d89-bf6e-499c-98fa-46f3b7f60025
```
  - 23.kmac_test_vectors_shake_256.96084999064114673139453835659170344426505033267000747533932322182717669636174
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:15cd2a05-d548-4f00-9b85-e1da8ed64db7
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 2.kmac_test_vectors_sha3_256.97398334358186092718693290603450851085172520981548139161285664971067882604992
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  24972076 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  24972076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 27.kmac_test_vectors_sha3_384.81062049746391434158390675505069101638979365469338819190843669796057955997994
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  72759891 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  72759891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 42.kmac_test_vectors_shake_128.46580188182915903316036361560283031529626173642974903583201562620271939209121
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  51533508 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  51533508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac has 1 failures.
  - 42.kmac_test_vectors_kmac.111017242884378502642812145126958268802989884571377084917801134812566137251958
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  34655400 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  34655400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 44.kmac_test_vectors_sha3_512.109159804250754826575930106760699389985587315509633507093683251431491242263712
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @  25763088 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  25763088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.72093913371593812495058792307306234820413309979473417289259304347436423305200
    Line 953, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32907905453 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 32907905453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.86014870108473959952452743093560750339762087055813154569832911742741029937878
    Line 347, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10006337098 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 10006337098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 1.kmac_app_with_partial_data.60252447548403905671646734342694270465490036316864867580410739032698765314526
    Line 323, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 601662932 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (77 [0x4d] vs 60 [0x3c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 601662932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 9.kmac_entropy_refresh.105169003067927510620453210612707953589158712545100318089946312401584578151398
    Line 963, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 26513343781 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (60 [0x3c] vs 144 [0x90]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 26513343781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 0.kmac_stress_all_with_rand_reset.32193248480018064130982708653059370782275829319700076969260654463929714966096
    Line 1030, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 59060358750 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 59060358750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 22.kmac_error.100507853737828396545189989748754063147375815888600975609039817926323810402764
    Line 771, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/MASKED Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`