KMAC/MASKED Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.572m	4.649ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	31.485us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	259.441us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.350s	1.445ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.730s	401.709us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.750s	85.086us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	259.441us	20	20	100.00
		kmac_csr_aliasing	9.730s	401.709us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	39.489us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	38.222us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.415h	74.953ms	43	50	86.00
V2	burst_write	kmac_burst_write	30.280m	39.740ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	58.845m	92.994ms	5	5	100.00
		kmac_test_vectors_sha3_256	53.227m	58.474ms	5	5	100.00
		kmac_test_vectors_sha3_384	40.317m	235.928ms	5	5	100.00
		kmac_test_vectors_sha3_512	28.927m	51.955ms	5	5	100.00
		kmac_test_vectors_shake_128	1.209h	320.419ms	5	5	100.00
		kmac_test_vectors_shake_256	59.548m	341.773ms	5	5	100.00
		kmac_test_vectors_kmac	2.930s	52.774us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.490s	81.177us	5	5	100.00
V2	sideload	kmac_sideload	9.768m	16.015ms	50	50	100.00
V2	app	kmac_app	8.758m	20.346ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.202m	135.814ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.698m	52.040ms	50	50	100.00
V2	error	kmac_error	10.645m	82.582ms	50	50	100.00
V2	key_error	kmac_key_error	15.340s	13.616ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	58.780s	1.707ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.830s	594.826us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.463m	31.046ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	23.920s	4.776ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.099h	262.079ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.890s	15.166us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	53.045us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.210s	2.100ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.210s	2.100ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	31.485us	5	5	100.00
		kmac_csr_rw	1.220s	259.441us	20	20	100.00
		kmac_csr_aliasing	9.730s	401.709us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	492.052us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	31.485us	5	5	100.00
		kmac_csr_rw	1.220s	259.441us	20	20	100.00
		kmac_csr_aliasing	9.730s	401.709us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	492.052us	20	20	100.00
V2		TOTAL			678	690	98.26
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.450s	132.719us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.450s	132.719us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.450s	132.719us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.450s	132.719us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.960s	145.818us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.967m	9.224ms	5	5	100.00
		kmac_tl_intg_err	5.530s	2.935ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.530s	2.935ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	23.920s	4.776ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.572m	4.649ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.768m	16.015ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.450s	132.719us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.967m	9.224ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.967m	9.224ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.967m	9.224ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.572m	4.649ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	23.920s	4.776ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.967m	9.224ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.748m	5.810ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.572m	4.649ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.164m	4.488ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			868	890	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.44	97.91	92.62	99.89	78.17	95.59	99.05	97.88

Failure Buckets

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test kmac_long_msg_and_output has 7 failures.
  - 3.kmac_long_msg_and_output.84593303850055900452578824709618554252275088512888048581105620073724184580934
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:7d912b29-45ac-42be-8848-4b3dec141a98
```
  - 20.kmac_long_msg_and_output.109280397213188318472843297729148434723072574071545534420983922506949593915870
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:c84d1a5e-ae0b-470d-9557-928c08362ad4
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app has 1 failures.

1.kmac_app.80223476806772302426123853948415446651332624367916759880652831208036038294219
Line 613, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app/latest/run.log

  UVM_FATAL @ 9254797765 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (188 [0xbc] vs 26 [0x1a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9254797765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

1.kmac_stress_all.89100115352391642678199923059191366638308817826378834995288140583195129412688
Line 437, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all/latest/run.log

  UVM_FATAL @ 11561764457 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (149 [0x95] vs 77 [0x4d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11561764457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_stress_all.110641251217143929659876576738113210940614374472474231575181437112144585182678
Line 737, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all/latest/run.log

  UVM_FATAL @ 35967901799 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (225 [0xe1] vs 52 [0x34]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 35967901799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app_with_partial_data has 1 failures.

3.kmac_app_with_partial_data.88414541381777974329213452132248466727485276483321085759704152252933769160557
Line 273, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 412363528 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (123 [0x7b] vs 197 [0xc5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 412363528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

8.kmac_mubi.55122932326873309688323971506211496435292932924611990957267058388958591891678
Line 519, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_mubi/latest/run.log

  UVM_FATAL @ 88153152924 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (93 [0x5d] vs 84 [0x54]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 88153152924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:848) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.52434631598014971633295135392870466663548405015591849027078289405755146016892
    Line 347, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1660744725 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1660744725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.114827207648113988009321118542241660005674306890979333219627993724962304685277
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2608283144 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2608283144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.72846234847380293707119812354526510169203536785643715647162585817116377552707
    Line 500, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1220019782 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1220019782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.40846302034888267959195060659691555379083780123162945375074339242507620955631
    Line 300, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 186799154 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 186799154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 14.kmac_key_error.35294620764594763360120509907824057149584107188366550459899089872762154206625
    Line 275, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 780946135 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 780946135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```