KMAC/MASKED Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.587m	6.363ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	66.386us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	378.665us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.440s	3.843ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.450s	10.364ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.640s	537.458us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	378.665us	20	20	100.00
		kmac_csr_aliasing	10.450s	10.364ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	13.330us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	42.092us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.455h	1.192s	44	50	88.00
V2	burst_write	kmac_burst_write	27.550m	30.020ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	59.446m	90.051ms	5	5	100.00
		kmac_test_vectors_sha3_256	1.008h	587.347ms	5	5	100.00
		kmac_test_vectors_sha3_384	40.162m	77.843ms	5	5	100.00
		kmac_test_vectors_sha3_512	30.816m	219.694ms	5	5	100.00
		kmac_test_vectors_shake_128	5.205m	145.900ms	5	5	100.00
		kmac_test_vectors_shake_256	47.455m	242.722ms	5	5	100.00
		kmac_test_vectors_kmac	3.410s	120.199us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.040s	224.829us	5	5	100.00
V2	sideload	kmac_sideload	9.918m	79.752ms	50	50	100.00
V2	app	kmac_app	7.126m	93.556ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.051m	8.073ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.319m	12.717ms	48	50	96.00
V2	error	kmac_error	9.352m	110.107ms	50	50	100.00
V2	key_error	kmac_key_error	14.330s	7.649ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	52.630s	8.871ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.400s	181.523us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.219m	6.409ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.300s	863.258us	50	50	100.00
V2	stress_all	kmac_stress_all	1.035h	143.193ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.860s	19.915us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	81.052us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.200s	676.095us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.200s	676.095us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	66.386us	5	5	100.00
		kmac_csr_rw	1.230s	378.665us	20	20	100.00
		kmac_csr_aliasing	10.450s	10.364ms	5	5	100.00
		kmac_same_csr_outstanding	2.760s	210.117us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	66.386us	5	5	100.00
		kmac_csr_rw	1.230s	378.665us	20	20	100.00
		kmac_csr_aliasing	10.450s	10.364ms	5	5	100.00
		kmac_same_csr_outstanding	2.760s	210.117us	20	20	100.00
V2		TOTAL			681	690	98.70
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	252.658us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	252.658us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	252.658us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	252.658us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.990s	171.052us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.660m	13.328ms	5	5	100.00
		kmac_tl_intg_err	5.040s	503.546us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.040s	503.546us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.300s	863.258us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.587m	6.363ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.918m	79.752ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	252.658us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.660m	13.328ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.660m	13.328ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.660m	13.328ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.587m	6.363ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.300s	863.258us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.660m	13.328ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.663m	17.889ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.587m	6.363ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.920m	49.280ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			876	890	98.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.34	97.91	92.62	99.89	77.46	95.59	99.05	97.88

Failure Buckets

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test kmac_long_msg_and_output has 6 failures.
  - 10.kmac_long_msg_and_output.47734493770217961381032766977906976863897974194752395097609458692258847256182
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:f74bbd74-bba9-41a3-928a-c8b6cc6c649b
```
  - 19.kmac_long_msg_and_output.82942174032576726521991406700641993012976638070565026398248867499486583339662
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:ddc0751c-f0c2-4455-9dce-62036ec64278
```
  - ... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.42252906886995292507863213141054591939161964366261533048766107062250924059227
    Line 470, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8650336030 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8650336030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.52448818469493646684935498008034254371896497164620253589196653211947785538759
    Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1023745394 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1023745394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_stress_all has 1 failures.

17.kmac_stress_all.39729270703552455485798306498984513794836581311789154223741598563691980553161
Line 351, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_stress_all/latest/run.log

  UVM_FATAL @ 1777808194 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (239 [0xef] vs 202 [0xca]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1777808194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

18.kmac_entropy_refresh.113914137810386451691732729778150398405015478994279266394540879681302300079885
Line 463, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5053699079 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (118 [0x76] vs 84 [0x54]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5053699079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.kmac_entropy_refresh.13017464836752888835564475310456512023431199220680395081583074497892377105978
Line 495, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 7630357726 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (158 [0x9e] vs 21 [0x15]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7630357726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 2.kmac_stress_all_with_rand_reset.72999841004538733913782916185497317444664473954071627940536846156188162238215
    Line 286, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 137253147 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 137253147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```