KMAC/UNMASKED Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.374m	19.632ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	110.745us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	29.144us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.270s	3.541ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.230s	1.036ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.450s	28.927us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	29.144us	20	20	100.00
		kmac_csr_aliasing	10.230s	1.036ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	20.672us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.530s	71.106us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.743m	711.273ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.043m	25.679ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.172m	195.860ms	50	50	100.00
		kmac_test_vectors_sha3_256	30.741m	366.921ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.286m	290.427ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.654m	267.015ms	50	50	100.00
		kmac_test_vectors_shake_128	1.434h	1.072s	50	50	100.00
		kmac_test_vectors_shake_256	1.187h	432.393ms	50	50	100.00
		kmac_test_vectors_kmac	5.920s	4.065ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.320s	1.562ms	50	50	100.00
V2	sideload	kmac_sideload	6.904m	31.226ms	50	50	100.00
V2	app	kmac_app	4.936m	70.429ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.611m	100.951ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.412m	66.841ms	50	50	100.00
V2	error	kmac_error	6.901m	83.736ms	50	50	100.00
V2	key_error	kmac_key_error	9.380s	14.074ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.440s	4.215ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.510s	8.633ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.157m	14.653ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	48.770s	3.871ms	50	50	100.00
V2	stress_all	kmac_stress_all	29.926m	253.202ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.870s	12.738us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	31.627us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.640s	590.896us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.640s	590.896us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	110.745us	5	5	100.00
		kmac_csr_rw	1.230s	29.144us	20	20	100.00
		kmac_csr_aliasing	10.230s	1.036ms	5	5	100.00
		kmac_same_csr_outstanding	2.930s	209.022us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	110.745us	5	5	100.00
		kmac_csr_rw	1.230s	29.144us	20	20	100.00
		kmac_csr_aliasing	10.230s	1.036ms	5	5	100.00
		kmac_same_csr_outstanding	2.930s	209.022us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.270s	231.435us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.270s	231.435us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.270s	231.435us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.270s	231.435us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.110s	268.264us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.197m	25.387ms	5	5	100.00
		kmac_tl_intg_err	5.330s	1.898ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.330s	1.898ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	48.770s	3.871ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.374m	19.632ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.904m	31.226ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.270s	231.435us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.197m	25.387ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.197m	25.387ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.197m	25.387ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.374m	19.632ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	48.770s	3.871ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.197m	25.387ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.304m	19.983ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.374m	19.632ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.606m	267.166ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			1274	1290	98.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.77	96.59	92.44	100.00	90.91	94.60	98.82	97.02

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 11 failures:

Test kmac_stress_all_with_rand_reset has 11 failures.

2.kmac_stress_all_with_rand_reset.2211327211
Line 1783, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 107516097644 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 107516097644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_stress_all_with_rand_reset.4117368693
Line 461, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20812364496 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 20812364496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_stress_all has 2 failures.

3.kmac_stress_all.2594744261
Line 260, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest/run.log

  UVM_FATAL @ 42458105066 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (227 [0xe3] vs 114 [0x72]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 42458105066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.kmac_stress_all.2386118347
Line 269, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest/run.log

  UVM_FATAL @ 1312038635 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (183 [0xb7] vs 147 [0x93]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1312038635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

13.kmac_app.1123928581
Line 241, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_app/latest/run.log

  UVM_FATAL @ 2156817708 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (58 [0x3a] vs 63 [0x3f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2156817708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 8.kmac_shadow_reg_errors_with_csr_rw.1831278202
    Line 232, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 179211931 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (848145008 [0x328daa70] vs 1545097852 [0x5c18527c]) Regname: kmac_reg_block.prefix_4 reset value: 0x0
  UVM_INFO @ 179211931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 27.kmac_burst_write.3095310967
    Line 300, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```