KMAC/UNMASKED Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: `748235cbb6`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.147m	4.226ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	113.376us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	36.120us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	26.250s	19.378ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.430s	3.104ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.230s	31.562us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	36.120us	20	20	100.00
		kmac_csr_aliasing	10.430s	3.104ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.730s	30.333us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.410s	39.631us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.218m	813.177ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.386m	69.902ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.534m	551.119ms	50	50	100.00
		kmac_test_vectors_sha3_256	31.550m	186.372ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.784m	584.605ms	50	50	100.00
		kmac_test_vectors_sha3_512	20.177m	972.854ms	50	50	100.00
		kmac_test_vectors_shake_128	1.479h	1.084s	50	50	100.00
		kmac_test_vectors_shake_256	1.276h	906.281ms	50	50	100.00
		kmac_test_vectors_kmac	5.280s	1.268ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.270s	967.254us	50	50	100.00
V2	sideload	kmac_sideload	7.245m	23.181ms	50	50	100.00
V2	app	kmac_app	4.682m	14.987ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.663m	92.317ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.901m	78.003ms	48	50	96.00
V2	error	kmac_error	7.429m	22.624ms	50	50	100.00
V2	key_error	kmac_key_error	7.240s	12.193ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.600s	8.399ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	36.220s	2.540ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.116m	16.554ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	40.700s	1.780ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.050m	353.318ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.790s	39.663us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	21.515us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.260s	575.278us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.260s	575.278us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	113.376us	5	5	100.00
		kmac_csr_rw	1.210s	36.120us	20	20	100.00
		kmac_csr_aliasing	10.430s	3.104ms	5	5	100.00
		kmac_same_csr_outstanding	2.880s	797.158us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	113.376us	5	5	100.00
		kmac_csr_rw	1.210s	36.120us	20	20	100.00
		kmac_csr_aliasing	10.430s	3.104ms	5	5	100.00
		kmac_same_csr_outstanding	2.880s	797.158us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.390s	72.886us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.390s	72.886us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.390s	72.886us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.390s	72.886us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.300s	1.270ms	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.303m	7.847ms	5	5	100.00
		kmac_tl_intg_err	5.150s	1.054ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.150s	1.054ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	40.700s	1.780ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.147m	4.226ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.245m	23.181ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.390s	72.886us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.303m	7.847ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.303m	7.847ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.303m	7.847ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.147m	4.226ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	40.700s	1.780ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.303m	7.847ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.867m	36.782ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.147m	4.226ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.580m	304.499ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			1274	1290	98.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.26	96.58	92.46	100.00	87.50	94.67	98.84	96.74

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 10 failures:
- Test kmac_stress_all_with_rand_reset has 10 failures.
  - 2.kmac_stress_all_with_rand_reset.30985438739616747752374529417601425825351300060173976938616678686699056347091
    Line 544, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25743862693 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 25743862693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.1101216614454030438474262312750299247161321096649127907724979107513969764127
    Line 766, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57205231374 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 57205231374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_stress_all_with_rand_reset has 1 failures.

13.kmac_stress_all_with_rand_reset.12017934691366812837588927335947934346411414649583577219878714996295142375558
Line 444, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10094097110 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (253 [0xfd] vs 118 [0x76]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10094097110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

18.kmac_entropy_refresh.97944075628918050604648917242777302728646450132349810045469304894269961942122
Line 321, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5712182054 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (228 [0xe4] vs 224 [0xe0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5712182054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

45.kmac_app.105203757694197506360652364872649308007812608005912593136136133643643260576351
Line 278, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_app/latest/run.log

  UVM_FATAL @ 3142339136 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (116 [0x74] vs 139 [0x8b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3142339136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 9.kmac_shadow_reg_errors_with_csr_rw.69673157194381515594756817384794392215297268048363303641066393709495826573357
    Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  43251505 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (533420533 [0x1fcb59f5] vs 2845479955 [0xa99a9413]) Regname: kmac_reg_block.prefix_6.prefix_0 reset value: 0x0
  UVM_INFO @  43251505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 18.kmac_stress_all_with_rand_reset.28114604130507790061068767251325011758678897163846400375819502331341222608075
    Line 765, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 72447184809 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (124 [0x7c] vs 255 [0xff]) Mismatch between exp_digest[44] and act_digest[44]
  UVM_INFO @ 72447184809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 35.kmac_entropy_refresh.86580067592566244251221947082752359335632404677520452053940725720738556728847
    Line 406, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```