KMAC/UNMASKED Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.060m	2.967ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	303.770us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.270s	454.308us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.760s	1.931ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.270s	3.803ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.670s	75.140us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.270s	454.308us	20	20	100.00
		kmac_csr_aliasing	10.270s	3.803ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	14.127us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.390s	264.575us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.613m	470.933ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.140m	59.581ms	46	50	92.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.238m	965.412ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.291m	363.902ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.365m	440.587ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.422m	49.414ms	50	50	100.00
		kmac_test_vectors_shake_128	1.849h	3.698s	50	50	100.00
		kmac_test_vectors_shake_256	1.265h	866.952ms	50	50	100.00
		kmac_test_vectors_kmac	5.260s	183.663us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.620s	994.609us	50	50	100.00
V2	sideload	kmac_sideload	7.493m	30.886ms	50	50	100.00
V2	app	kmac_app	5.700m	75.764ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.712m	15.950ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.056m	36.921ms	48	50	96.00
V2	error	kmac_error	7.547m	110.719ms	49	50	98.00
V2	key_error	kmac_key_error	8.420s	11.502ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	36.770s	8.384ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.060s	1.914ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.256m	92.928ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	39.740s	2.190ms	50	50	100.00
V2	stress_all	kmac_stress_all	45.391m	558.310ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.860s	26.002us	50	50	100.00
V2	alert_test	kmac_alert_test	0.850s	71.397us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.450s	145.586us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.450s	145.586us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	303.770us	5	5	100.00
		kmac_csr_rw	1.270s	454.308us	20	20	100.00
		kmac_csr_aliasing	10.270s	3.803ms	5	5	100.00
		kmac_same_csr_outstanding	2.720s	989.563us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	303.770us	5	5	100.00
		kmac_csr_rw	1.270s	454.308us	20	20	100.00
		kmac_csr_aliasing	10.270s	3.803ms	5	5	100.00
		kmac_same_csr_outstanding	2.720s	989.563us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	229.521us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	229.521us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	229.521us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	229.521us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.200s	278.614us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.033m	4.803ms	5	5	100.00
		kmac_tl_intg_err	5.690s	1.206ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.690s	1.206ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.740s	2.190ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.060m	2.967ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.493m	30.886ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	229.521us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.033m	4.803ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.033m	4.803ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.033m	4.803ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.060m	2.967ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.740s	2.190ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.033m	4.803ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.263m	3.874ms	8	10	80.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.060m	2.967ms	50	50	100.00
V2S		TOTAL			73	75	97.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	53.232m	458.254ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			1245	1290	96.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.21	96.25	92.34	100.00	87.50	94.66	98.84	96.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:788) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test kmac_stress_all_with_rand_reset has 31 failures.
  - 0.kmac_stress_all_with_rand_reset.16225886256613119655605314412369339925222031073692123061407983362555465882387
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 105052262 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 105052262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.64049577059761969398306626763322248892224053743672206725131340029273763079811
    Line 481, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23314013535 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 23314013535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_entropy_refresh has 2 failures.

1.kmac_entropy_refresh.72132348554481867908812779026467870805920627080836856822257025023254510825374
Line 301, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 1979008662 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (171 [0xab] vs 168 [0xa8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1979008662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.kmac_entropy_refresh.88828548671234844478427044962634092866171319659363408279369603276477206051675
Line 587, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 6483064691 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (86 [0x56] vs 208 [0xd0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6483064691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 2 failures.

1.kmac_mubi.38338101750135099498448192871826380154688895775939670664479279174433116045742
Line 545, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_mubi/latest/run.log

  UVM_FATAL @ 21933541627 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (226 [0xe2] vs 68 [0x44]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 21933541627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_mubi.102163168927925449854088942749441421607385565254841837905145167492127670779678
Line 381, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_mubi/latest/run.log

  UVM_FATAL @ 2398561990 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (29 [0x1d] vs 161 [0xa1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2398561990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_error has 1 failures.

39.kmac_error.102474488292149174594949413451038953267346427924150052118111474181798313247351
Line 521, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_error/latest/run.log

  UVM_FATAL @ 2652310676 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (80 [0x50] vs 139 [0x8b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2652310676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 10.kmac_stress_all_with_rand_reset.58524859264504014404371456100398969758075389887427545217410783010793621137351
    Line 807, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8108235247 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 8108235247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.kmac_stress_all_with_rand_reset.100619303556487545502359870497356634015502846137298181201548721051198499136405
    Line 645, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7910987755 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 7910987755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 4 failures.
  - 16.kmac_burst_write.69019538385483398740001143824804316938063478427154450738935434573322918247898
    Line 572, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.kmac_burst_write.14388940411925743763555222636263347498081494125418189114742775961461626508555
    Line 1052, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.