4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | kmac_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | kmac_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | kmac_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0 | 20 | 0.00 | ||
| kmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | kmac_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | kmac_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 115 | 0.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 0 | 50 | 0.00 | ||
| V2 | burst_write | kmac_burst_write | 0 | 50 | 0.00 | ||
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 0 | 50 | 0.00 | ||
| kmac_test_vectors_sha3_256 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_sha3_384 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_sha3_512 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_shake_128 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_shake_256 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_kmac | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_kmac_xof | 0 | 50 | 0.00 | ||||
| V2 | sideload | kmac_sideload | 0 | 50 | 0.00 | ||
| V2 | app | kmac_app | 0 | 50 | 0.00 | ||
| V2 | app_with_partial_data | kmac_app_with_partial_data | 0 | 10 | 0.00 | ||
| V2 | entropy_refresh | kmac_entropy_refresh | 0 | 50 | 0.00 | ||
| V2 | error | kmac_error | 0 | 50 | 0.00 | ||
| V2 | key_error | kmac_key_error | 0 | 50 | 0.00 | ||
| V2 | edn_timeout_error | kmac_edn_timeout_error | 0 | 20 | 0.00 | ||
| V2 | entropy_mode_error | kmac_entropy_mode_error | 0 | 20 | 0.00 | ||
| V2 | entropy_ready_error | kmac_entropy_ready_error | 0 | 10 | 0.00 | ||
| V2 | lc_escalation | kmac_lc_escalation | 0 | 50 | 0.00 | ||
| V2 | stress_all | kmac_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | kmac_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | kmac_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | kmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| kmac_csr_rw | 0 | 20 | 0.00 | ||||
| kmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| kmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| kmac_csr_rw | 0 | 20 | 0.00 | ||||
| kmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| kmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 1050 | 0.00 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | kmac_sec_cm | 0 | 5 | 0.00 | ||
| kmac_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sideload | kmac_sideload | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 0 | 10 | 0.00 | ||
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 0 | 75 | 0.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 1290 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 0 | 0.00 |
| V2 | 25 | 25 | 0 | 0.00 |
| V2S | 5 | 5 | 0 | 0.00 |
| V3 | 2 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1292 failures:
0.kmac_smoke.61161977887530638074988087549302970093481751842339275865202565575718620427205
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_smoke/latest/run.log
1.kmac_smoke.60013108379197727071032460605232820399677240935474676631004992628530439021865
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_smoke/latest/run.log
... and 48 more failures.
0.kmac_long_msg_and_output.66201876388414433124487231191048142689024864010933651729371529008838061502426
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log
1.kmac_long_msg_and_output.47509387193595580196341000378003365277299335102612221478770262767458990828166
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
... and 48 more failures.
0.kmac_sideload.91366842282366226359904668815346288464805359492622836234204255251696969042210
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_sideload/latest/run.log
1.kmac_sideload.35700535556555621429854751764590732227319651783908650108030330164831070993931
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_sideload/latest/run.log
... and 48 more failures.
0.kmac_burst_write.4151591256463725434920889497700709015357065807249060190844368477355213119367
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest/run.log
1.kmac_burst_write.80541165862063142321567452615264661595448009560517668868215954324178077118853
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest/run.log
... and 48 more failures.
0.kmac_test_vectors_sha3_224.71192106890506187467549109472478111690426247153894281538856633223624550149798
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log
1.kmac_test_vectors_sha3_224.39264408708342778285962099810665448314471010810006999212207683362519275265654
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.