KMAC/UNMASKED Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.131m	7.577ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.250s	139.345us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	269.932us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.160s	2.033ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.410s	2.055ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.150s	45.456us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	269.932us	20	20	100.00
		kmac_csr_aliasing	11.410s	2.055ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	27.100us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	151.855us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.564m	2.504s	50	50	100.00
V2	burst_write	kmac_burst_write	13.271m	74.105ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.903m	202.519ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.675m	186.803ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.645m	795.310ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.671m	207.290ms	50	50	100.00
		kmac_test_vectors_shake_128	1.578h	2.135s	50	50	100.00
		kmac_test_vectors_shake_256	1.277h	1.824s	50	50	100.00
		kmac_test_vectors_kmac	6.240s	4.670ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.570s	1.028ms	50	50	100.00
V2	sideload	kmac_sideload	7.970m	22.545ms	49	50	98.00
V2	app	kmac_app	5.313m	57.351ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.517m	21.599ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	5.566m	13.526ms	49	50	98.00
V2	error	kmac_error	6.195m	63.540ms	50	50	100.00
V2	key_error	kmac_key_error	10.840s	17.036ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.390s	7.046ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	33.130s	2.227ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	47.360s	3.812ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	34.650s	2.892ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.397m	106.302ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	29.883us	50	50	100.00
V2	alert_test	kmac_alert_test	0.840s	64.481us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.030s	209.484us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.030s	209.484us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.250s	139.345us	5	5	100.00
		kmac_csr_rw	1.210s	269.932us	20	20	100.00
		kmac_csr_aliasing	11.410s	2.055ms	5	5	100.00
		kmac_same_csr_outstanding	3.140s	447.752us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.250s	139.345us	5	5	100.00
		kmac_csr_rw	1.210s	269.932us	20	20	100.00
		kmac_csr_aliasing	11.410s	2.055ms	5	5	100.00
		kmac_same_csr_outstanding	3.140s	447.752us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.520s	61.035us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.520s	61.035us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.520s	61.035us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.520s	61.035us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.870s	103.902us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.117m	5.271ms	5	5	100.00
		kmac_tl_intg_err	6.020s	1.012ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.020s	1.012ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	34.650s	2.892ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.131m	7.577ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.970m	22.545ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.520s	61.035us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.117m	5.271ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.117m	5.271ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.117m	5.271ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.131m	7.577ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	34.650s	2.892ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.117m	5.271ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.743m	36.003ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.131m	7.577ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	51.584m	327.324ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1275	1290	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.30	96.58	92.45	100.00	87.50	94.67	98.84	97.02

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 11.kmac_stress_all_with_rand_reset.57406752926857292275254092844711973406996309459016613997286568975285196537317
    Line 367, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16256276319 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 16256276319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.kmac_stress_all_with_rand_reset.73599511185005704801150987113612422585754977270624552710221828539530719597019
    Line 1899, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 113467646022 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 113467646022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_entropy_refresh has 1 failures.

1.kmac_entropy_refresh.71238813871185898745982963512104393649500884262209961646721418937184657595431
Line 529, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5735144215 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (66 [0x42] vs 116 [0x74]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5735144215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

2.kmac_app.84536298934494296181622475398121766751217049017152455818353360958578221503419
Line 937, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_app/latest/run.log

  UVM_FATAL @ 12449109855 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (44 [0x2c] vs 170 [0xaa]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 12449109855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app_with_partial_data has 1 failures.

5.kmac_app_with_partial_data.86119781711291135976885166328689816533506240212582790711566858853461983543552
Line 475, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 10617799159 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (13 [0xd] vs 86 [0x56]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10617799159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

10.kmac_stress_all.80300105379667874817918670367698965386072899561401269678031207891462477390684
Line 723, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest/run.log

  UVM_FATAL @ 6651319854 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (147 [0x93] vs 198 [0xc6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6651319854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 7.kmac_shadow_reg_errors_with_csr_rw.35739454483835500999746748643055945582119889356036910438904667934067642882106
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  66082173 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (2578329376 [0x99ae2f20] vs 0 [0x0]) Regname: kmac_reg_block.prefix_4.prefix_0 reset value: 0x0
  UVM_INFO @  66082173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_sideload has 1 failures.
  - 24.kmac_sideload.10183733229904378087861057563647784321182917062680058840540586780596664754961
    Line 1238, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```