KMAC/UNMASKED Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.252m	10.781ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	28.739us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	30.651us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.240s	9.612ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.770s	448.167us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.210s	108.389us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	30.651us	20	20	100.00
		kmac_csr_aliasing	9.770s	448.167us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	100.977us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	122.400us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.750m	98.399ms	50	50	100.00
V2	burst_write	kmac_burst_write	12.711m	105.012ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.596m	258.049ms	50	50	100.00
		kmac_test_vectors_sha3_256	36.808m	1.305s	50	50	100.00
		kmac_test_vectors_sha3_384	27.075m	292.929ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.034m	246.259ms	50	50	100.00
		kmac_test_vectors_shake_128	1.744h	2.357s	49	50	98.00
		kmac_test_vectors_shake_256	1.255h	896.402ms	50	50	100.00
		kmac_test_vectors_kmac	5.700s	976.612us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.500s	2.231ms	50	50	100.00
V2	sideload	kmac_sideload	7.548m	85.408ms	50	50	100.00
V2	app	kmac_app	5.843m	18.933ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.218m	19.269ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.557m	104.860ms	50	50	100.00
V2	error	kmac_error	7.492m	30.410ms	50	50	100.00
V2	key_error	kmac_key_error	7.360s	4.506ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.490s	4.395ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.940s	2.181ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.137m	32.640ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	39.560s	4.814ms	50	50	100.00
V2	stress_all	kmac_stress_all	38.456m	304.320ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.830s	13.926us	50	50	100.00
V2	alert_test	kmac_alert_test	0.870s	23.333us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.050s	167.180us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.050s	167.180us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	28.739us	5	5	100.00
		kmac_csr_rw	1.220s	30.651us	20	20	100.00
		kmac_csr_aliasing	9.770s	448.167us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	133.790us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	28.739us	5	5	100.00
		kmac_csr_rw	1.220s	30.651us	20	20	100.00
		kmac_csr_aliasing	9.770s	448.167us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	133.790us	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.380s	603.070us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.380s	603.070us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.380s	603.070us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.380s	603.070us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.390s	918.017us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.628m	62.314ms	5	5	100.00
		kmac_tl_intg_err	6.190s	2.978ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.190s	2.978ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.560s	4.814ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.252m	10.781ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.548m	85.408ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.380s	603.070us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.628m	62.314ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.628m	62.314ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.628m	62.314ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.252m	10.781ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.560s	4.814ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.628m	62.314ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.111m	98.283ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.252m	10.781ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.012h	204.358ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1282	1290	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	96.58	92.45	100.00	89.77	94.67	98.84	97.16

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 5.kmac_stress_all_with_rand_reset.38929273380340799856647565293212400174570644818021175480326564090203451900847
    Line 1772, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 283549438332 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 283549438332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.kmac_stress_all_with_rand_reset.30790200116529188733628758507198285161599370844664636787464257093815471758006
    Line 733, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 101053615531 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 101053615531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test kmac_test_vectors_shake_128 has 1 failures.

26.kmac_test_vectors_shake_128.80351359901617925254351248999359518614957609134889601491785473017655480459247
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_test_vectors_shake_128/latest/run.log

  [make]: simulate
  cd /workspace/26.kmac_test_vectors_shake_128/latest && /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531958767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.2531958767 +enable_masking=0 +sw_key_masked=0
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Feb  4 14:03 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 28.kmac_key_error.2571862326149233777997485548940475854615356780739311606767654150269534173442
    Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 1099874784 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 1099874784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'host_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 48.kmac_stress_all_with_rand_reset.55535564154990117218605264094064690200899186422130676571487826555239431253211
    Line 1746, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 83506717823 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_kmac_app_agent[2].m_data_push_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_kmac_app_agent[2].m_data_push_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.kmac_app_vseq.kmac_app_seq.host_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 83506717823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```