KMAC/UNMASKED Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.154m	17.944ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	62.294us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	142.410us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.530s	4.539ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.570s	615.664us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.820s	40.199us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	142.410us	20	20	100.00
		kmac_csr_aliasing	11.570s	615.664us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	20.069us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.410s	38.740us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	46.834m	127.928ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.385m	145.882ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.960m	758.204ms	50	50	100.00
		kmac_test_vectors_sha3_256	32.890m	384.416ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.178m	256.287ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.223m	260.952ms	50	50	100.00
		kmac_test_vectors_shake_128	1.587h	2.121s	50	50	100.00
		kmac_test_vectors_shake_256	1.278h	213.313ms	50	50	100.00
		kmac_test_vectors_kmac	5.390s	1.569ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.550s	1.049ms	50	50	100.00
V2	sideload	kmac_sideload	7.090m	15.784ms	48	50	96.00
V2	app	kmac_app	6.208m	142.157ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.996m	14.057ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.386m	65.370ms	48	50	96.00
V2	error	kmac_error	7.480m	25.139ms	50	50	100.00
V2	key_error	kmac_key_error	6.770s	3.808ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.420s	5.576ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.820s	2.746ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.165m	27.057ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	42.500s	941.722us	50	50	100.00
V2	stress_all	kmac_stress_all	38.081m	142.010ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.840s	22.227us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	161.594us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.770s	138.357us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.770s	138.357us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	62.294us	5	5	100.00
		kmac_csr_rw	1.230s	142.410us	20	20	100.00
		kmac_csr_aliasing	11.570s	615.664us	5	5	100.00
		kmac_same_csr_outstanding	2.780s	508.611us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	62.294us	5	5	100.00
		kmac_csr_rw	1.230s	142.410us	20	20	100.00
		kmac_csr_aliasing	11.570s	615.664us	5	5	100.00
		kmac_same_csr_outstanding	2.780s	508.611us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.350s	136.246us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.350s	136.246us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.350s	136.246us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.350s	136.246us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.130s	470.666us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.176m	61.747ms	5	5	100.00
		kmac_tl_intg_err	5.490s	488.016us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.490s	488.016us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	42.500s	941.722us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.154m	17.944ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.090m	15.784ms	48	50	96.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.350s	136.246us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.176m	61.747ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.176m	61.747ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.176m	61.747ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.154m	17.944ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	42.500s	941.722us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.176m	61.747ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.137m	117.428ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.154m	17.944ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	42.451m	99.791ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			1243	1290	96.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.27	96.58	92.45	100.00	87.50	94.67	98.84	96.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 36 failures:
- Test kmac_stress_all_with_rand_reset has 36 failures.
  - 1.kmac_stress_all_with_rand_reset.2652280412715761146492999145844356616886047534812953810202992186012787423889
    Line 769, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18798216306 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 18798216306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.93597390675787373879499176476251732715240404018275477109054534783666510077497
    Line 471, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9437167199 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 9437167199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]

has 5 failures:

Test kmac_entropy_refresh has 2 failures.

9.kmac_entropy_refresh.86248219025936084431308309327827696754751380516506189324700450188547910376574
Line 565, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 7610258752 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (127 [0x7f] vs 56 [0x38]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7610258752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.kmac_entropy_refresh.95757882175599715291044265370271419550629309273474319309447531738845369221962
Line 645, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 16928220145 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (195 [0xc3] vs 147 [0x93]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16928220145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 3 failures.

12.kmac_stress_all.29593025122975137816942333949428567285921018222377544827376812061470349936323
Line 503, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest/run.log

  UVM_FATAL @ 4850734589 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (185 [0xb9] vs 246 [0xf6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4850734589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.kmac_stress_all.7886704213884188372623033156914846785893117048682391406275832488492813992912
Line 1275, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest/run.log

  UVM_FATAL @ 17761027107 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (97 [0x61] vs 218 [0xda]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17761027107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 3.kmac_stress_all_with_rand_reset.113754047887056890863601694493782269762675461355421240471475804338981769225753
    Line 894, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43400500941 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 43400500941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.14882282481846489309786482456066235604457367939326112921317773614674311067170
    Line 272, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 676087796 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 676087796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_sideload has 2 failures.
  - 23.kmac_sideload.18572065958688090414568999712380475202905236391374660660787023704215162063317
    Line 1257, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.kmac_sideload.82320820277990814911102611108959881780362172964803696654846749187598707151812
    Line 1136, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```